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shawn1221Lorenzo Pieralisi
shawn1221
authored and
Lorenzo Pieralisi
committed
PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT
Most of the DT properties are used for both of RC driver and EP driver, so split them out in a new function, rockchip_pcie_parse_dt(), in pcie-rockchip.c and rename the original function to rockchip_pcie_parse_host_dt() to avoid confusion. No functional changed intended. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Tested-by: Jeffy Chen <[email protected]>
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3 files changed

+136
-114
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‎drivers/pci/host/pcie-rockchip-host.c

Lines changed: 5 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -705,130 +705,20 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)
705705
}
706706

707707
/**
708-
* rockchip_pcie_parse_dt - Parse Device Tree
708+
* rockchip_pcie_parse_host_dt - Parse Device Tree
709709
* @rockchip: PCIe port information
710710
*
711711
* Return: '0' on success and error value on failure
712712
*/
713-
static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
713+
static int rockchip_pcie_parse_host_dt(struct rockchip_pcie *rockchip)
714714
{
715715
struct device *dev = rockchip->dev;
716-
struct platform_device *pdev = to_platform_device(dev);
717-
struct device_node *node = dev->of_node;
718-
struct resource *regs;
719716
int err;
720717

721-
regs = platform_get_resource_byname(pdev,
722-
IORESOURCE_MEM,
723-
"axi-base");
724-
rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
725-
if (IS_ERR(rockchip->reg_base))
726-
return PTR_ERR(rockchip->reg_base);
727-
728-
regs = platform_get_resource_byname(pdev,
729-
IORESOURCE_MEM,
730-
"apb-base");
731-
rockchip->apb_base = devm_ioremap_resource(dev, regs);
732-
if (IS_ERR(rockchip->apb_base))
733-
return PTR_ERR(rockchip->apb_base);
734-
735-
err = rockchip_pcie_get_phys(rockchip);
718+
err = rockchip_pcie_parse_dt(rockchip);
736719
if (err)
737720
return err;
738721

739-
rockchip->lanes = 1;
740-
err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
741-
if (!err && (rockchip->lanes == 0 ||
742-
rockchip->lanes == 3 ||
743-
rockchip->lanes > 4)) {
744-
dev_warn(dev, "invalid num-lanes, default to use one lane\n");
745-
rockchip->lanes = 1;
746-
}
747-
748-
rockchip->link_gen = of_pci_get_max_link_speed(node);
749-
if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
750-
rockchip->link_gen = 2;
751-
752-
rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
753-
if (IS_ERR(rockchip->core_rst)) {
754-
if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
755-
dev_err(dev, "missing core reset property in node\n");
756-
return PTR_ERR(rockchip->core_rst);
757-
}
758-
759-
rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
760-
if (IS_ERR(rockchip->mgmt_rst)) {
761-
if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
762-
dev_err(dev, "missing mgmt reset property in node\n");
763-
return PTR_ERR(rockchip->mgmt_rst);
764-
}
765-
766-
rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
767-
"mgmt-sticky");
768-
if (IS_ERR(rockchip->mgmt_sticky_rst)) {
769-
if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
770-
dev_err(dev, "missing mgmt-sticky reset property in node\n");
771-
return PTR_ERR(rockchip->mgmt_sticky_rst);
772-
}
773-
774-
rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
775-
if (IS_ERR(rockchip->pipe_rst)) {
776-
if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
777-
dev_err(dev, "missing pipe reset property in node\n");
778-
return PTR_ERR(rockchip->pipe_rst);
779-
}
780-
781-
rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
782-
if (IS_ERR(rockchip->pm_rst)) {
783-
if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
784-
dev_err(dev, "missing pm reset property in node\n");
785-
return PTR_ERR(rockchip->pm_rst);
786-
}
787-
788-
rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
789-
if (IS_ERR(rockchip->pclk_rst)) {
790-
if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
791-
dev_err(dev, "missing pclk reset property in node\n");
792-
return PTR_ERR(rockchip->pclk_rst);
793-
}
794-
795-
rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
796-
if (IS_ERR(rockchip->aclk_rst)) {
797-
if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
798-
dev_err(dev, "missing aclk reset property in node\n");
799-
return PTR_ERR(rockchip->aclk_rst);
800-
}
801-
802-
rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
803-
if (IS_ERR(rockchip->ep_gpio)) {
804-
dev_err(dev, "missing ep-gpios property in node\n");
805-
return PTR_ERR(rockchip->ep_gpio);
806-
}
807-
808-
rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
809-
if (IS_ERR(rockchip->aclk_pcie)) {
810-
dev_err(dev, "aclk clock not found\n");
811-
return PTR_ERR(rockchip->aclk_pcie);
812-
}
813-
814-
rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
815-
if (IS_ERR(rockchip->aclk_perf_pcie)) {
816-
dev_err(dev, "aclk_perf clock not found\n");
817-
return PTR_ERR(rockchip->aclk_perf_pcie);
818-
}
819-
820-
rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
821-
if (IS_ERR(rockchip->hclk_pcie)) {
822-
dev_err(dev, "hclk clock not found\n");
823-
return PTR_ERR(rockchip->hclk_pcie);
824-
}
825-
826-
rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
827-
if (IS_ERR(rockchip->clk_pcie_pm)) {
828-
dev_err(dev, "pm clock not found\n");
829-
return PTR_ERR(rockchip->clk_pcie_pm);
830-
}
831-
832722
err = rockchip_pcie_setup_irq(rockchip);
833723
if (err)
834724
return err;
@@ -1195,8 +1085,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
11951085

11961086
platform_set_drvdata(pdev, rockchip);
11971087
rockchip->dev = dev;
1088+
rockchip->is_rc = true;
11981089

1199-
err = rockchip_pcie_parse_dt(rockchip);
1090+
err = rockchip_pcie_parse_host_dt(rockchip);
12001091
if (err)
12011092
return err;
12021093

‎drivers/pci/host/pcie-rockchip.c

Lines changed: 129 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,139 @@
1212
*/
1313

1414
#include <linux/clk.h>
15+
#include <linux/gpio/consumer.h>
16+
#include <linux/of_pci.h>
1517
#include <linux/phy/phy.h>
18+
#include <linux/platform_device.h>
19+
#include <linux/reset.h>
1620

1721
#include "pcie-rockchip.h"
1822

23+
int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
24+
{
25+
struct device *dev = rockchip->dev;
26+
struct platform_device *pdev = to_platform_device(dev);
27+
struct device_node *node = dev->of_node;
28+
struct resource *regs;
29+
int err;
30+
31+
regs = platform_get_resource_byname(pdev,
32+
IORESOURCE_MEM,
33+
"axi-base");
34+
rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
35+
if (IS_ERR(rockchip->reg_base))
36+
return PTR_ERR(rockchip->reg_base);
37+
38+
regs = platform_get_resource_byname(pdev,
39+
IORESOURCE_MEM,
40+
"apb-base");
41+
rockchip->apb_base = devm_ioremap_resource(dev, regs);
42+
if (IS_ERR(rockchip->apb_base))
43+
return PTR_ERR(rockchip->apb_base);
44+
45+
err = rockchip_pcie_get_phys(rockchip);
46+
if (err)
47+
return err;
48+
49+
rockchip->lanes = 1;
50+
err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
51+
if (!err && (rockchip->lanes == 0 ||
52+
rockchip->lanes == 3 ||
53+
rockchip->lanes > 4)) {
54+
dev_warn(dev, "invalid num-lanes, default to use one lane\n");
55+
rockchip->lanes = 1;
56+
}
57+
58+
rockchip->link_gen = of_pci_get_max_link_speed(node);
59+
if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
60+
rockchip->link_gen = 2;
61+
62+
rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
63+
if (IS_ERR(rockchip->core_rst)) {
64+
if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
65+
dev_err(dev, "missing core reset property in node\n");
66+
return PTR_ERR(rockchip->core_rst);
67+
}
68+
69+
rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
70+
if (IS_ERR(rockchip->mgmt_rst)) {
71+
if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
72+
dev_err(dev, "missing mgmt reset property in node\n");
73+
return PTR_ERR(rockchip->mgmt_rst);
74+
}
75+
76+
rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
77+
"mgmt-sticky");
78+
if (IS_ERR(rockchip->mgmt_sticky_rst)) {
79+
if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
80+
dev_err(dev, "missing mgmt-sticky reset property in node\n");
81+
return PTR_ERR(rockchip->mgmt_sticky_rst);
82+
}
83+
84+
rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
85+
if (IS_ERR(rockchip->pipe_rst)) {
86+
if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
87+
dev_err(dev, "missing pipe reset property in node\n");
88+
return PTR_ERR(rockchip->pipe_rst);
89+
}
90+
91+
rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
92+
if (IS_ERR(rockchip->pm_rst)) {
93+
if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
94+
dev_err(dev, "missing pm reset property in node\n");
95+
return PTR_ERR(rockchip->pm_rst);
96+
}
97+
98+
rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
99+
if (IS_ERR(rockchip->pclk_rst)) {
100+
if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
101+
dev_err(dev, "missing pclk reset property in node\n");
102+
return PTR_ERR(rockchip->pclk_rst);
103+
}
104+
105+
rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
106+
if (IS_ERR(rockchip->aclk_rst)) {
107+
if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
108+
dev_err(dev, "missing aclk reset property in node\n");
109+
return PTR_ERR(rockchip->aclk_rst);
110+
}
111+
112+
if (rockchip->is_rc) {
113+
rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
114+
if (IS_ERR(rockchip->ep_gpio)) {
115+
dev_err(dev, "missing ep-gpios property in node\n");
116+
return PTR_ERR(rockchip->ep_gpio);
117+
}
118+
}
119+
120+
rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
121+
if (IS_ERR(rockchip->aclk_pcie)) {
122+
dev_err(dev, "aclk clock not found\n");
123+
return PTR_ERR(rockchip->aclk_pcie);
124+
}
125+
126+
rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
127+
if (IS_ERR(rockchip->aclk_perf_pcie)) {
128+
dev_err(dev, "aclk_perf clock not found\n");
129+
return PTR_ERR(rockchip->aclk_perf_pcie);
130+
}
131+
132+
rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
133+
if (IS_ERR(rockchip->hclk_pcie)) {
134+
dev_err(dev, "hclk clock not found\n");
135+
return PTR_ERR(rockchip->hclk_pcie);
136+
}
137+
138+
rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
139+
if (IS_ERR(rockchip->clk_pcie_pm)) {
140+
dev_err(dev, "pm clock not found\n");
141+
return PTR_ERR(rockchip->clk_pcie_pm);
142+
}
143+
144+
return 0;
145+
}
146+
EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
147+
19148
int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
20149
{
21150
struct device *dev = rockchip->dev;

‎drivers/pci/host/pcie-rockchip.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,7 @@ struct rockchip_pcie {
222222
u32 mem_size;
223223
phys_addr_t msg_bus_addr;
224224
phys_addr_t mem_bus_addr;
225+
bool is_rc;
225226
};
226227

227228
static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
@@ -235,6 +236,7 @@ static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
235236
writel(val, rockchip->apb_base + reg);
236237
}
237238

239+
int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip);
238240
int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);
239241
void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);
240242
int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);

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