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Merge tag 'pinctrl-v3.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin-control fixes from Linus Walleij: "This kernel cycle has been calm for both pin control and GPIO so far but here are three pin control patches for you anyway, only really dealing with Baytrail: - Two fixes for the Baytrail driver affecting IRQs and output state in sysfs - Use the linux-gpio mailing list also for pinctrl patches" * tag 'pinctrl-v3.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: baytrail: show output gpio state correctly on Intel Baytrail pinctrl: use linux-gpio mailing list pinctrl: baytrail: Clear DIRECT_IRQ bit
2 parents f3ed88a + d90c338 commit 980d0d5

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MAINTAINERS

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Original file line numberDiff line numberDiff line change
@@ -7180,6 +7180,7 @@ F: drivers/crypto/picoxcell*
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PIN CONTROL SUBSYSTEM
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M: Linus Walleij <[email protected]>
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S: Maintained
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F: drivers/pinctrl/
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F: include/linux/pinctrl/

drivers/pinctrl/pinctrl-baytrail.c

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@@ -227,10 +227,14 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
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spin_lock_irqsave(&vg->lock, flags);
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value = readl(reg);
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WARN(value & BYT_DIRECT_IRQ_EN,
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"Bad pad config for io mode, force direct_irq_en bit clearing");
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/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
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* are used to indicate high and low level triggering
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*/
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value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
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value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
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BYT_TRIG_LVL);
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switch (type) {
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case IRQ_TYPE_LEVEL_HIGH:
@@ -318,7 +322,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
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"Potential Error: Setting GPIO with direct_irq_en to output");
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reg_val = readl(reg) | BYT_DIR_MASK;
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reg_val &= ~BYT_OUTPUT_EN;
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reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
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if (value)
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writel(reg_val | BYT_LEVEL, reg);

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