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torvaldstorvalds
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Fixes all over the place: - amdkfd: two static checker fixes - mst: a bunch of static checker and spec/hw interaction fixes - amdgpu: fix Iceland hw properly, and some fiji bugs, along with some write-combining fixes. - exynos: some regression fixes - adv7511: fix some EDID reading issues" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (38 commits) drm/dp/mst: deallocate payload on port destruction drm/dp/mst: Reverse order of MST enable and clearing VC payload table. drm/dp/mst: move GUID storage from mgr, port to only mst branch drm/dp/mst: change MST detection scheme drm/dp/mst: Calculate MST PBN with 31.32 fixed point drm: Add drm_fixp_from_fraction and drm_fixp2int_ceil drm/mst: Add range check for max_payloads during init drm/mst: Don't ignore the MST PBN self-test result drm: fix missing reference counting decrease drm/amdgpu: disable uvd and vce clockgating on Fiji drm/amdgpu: remove exp hardware support from iceland drm/amdgpu: load MEC ucode manually on iceland drm/amdgpu: don't load MEC2 on topaz drm/amdgpu: drop topaz support from gmc8 module drm/amdgpu: pull topaz gmc bits into gmc_v7 drm/amdgpu: The VI specific EXE bit should only apply to GMC v8.0 above drm/amdgpu: iceland use CI based MC IP drm/amdgpu: move gmc7 support out of CIK dependency drm/amdgpu/gfx7: enable cp inst/reg error interrupts drm/amdgpu/gfx8: enable cp inst/reg error interrupts ...
2 parents 22f6070 + 6739b3d commit 9b10882

28 files changed

+461
-252
lines changed

‎drivers/gpu/drm/amd/amdgpu/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
2525
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
2626

2727
# add asic specific block
28-
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o gmc_v7_0.o cik_ih.o kv_smc.o kv_dpm.o \
28+
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
2929
ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \
3030
amdgpu_amdkfd_gfx_v7.o
3131

@@ -34,6 +34,7 @@ amdgpu-y += \
3434

3535
# add GMC block
3636
amdgpu-y += \
37+
gmc_v7_0.o \
3738
gmc_v8_0.o
3839

3940
# add IH block

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
154154
.get_fw_version = get_fw_version
155155
};
156156

157-
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions()
157+
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
158158
{
159159
return (struct kfd2kgd_calls *)&kfd2kgd;
160160
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
115115
.get_fw_version = get_fw_version
116116
};
117117

118-
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions()
118+
struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
119119
{
120120
return (struct kfd2kgd_calls *)&kfd2kgd;
121121
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -256,11 +256,11 @@ static struct pci_device_id pciidlist[] = {
256256
{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
257257
#endif
258258
/* topaz */
259-
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
260-
{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
261-
{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
262-
{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
263-
{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
259+
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
260+
{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
261+
{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
262+
{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
263+
{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
264264
/* tonga */
265265
{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
266266
{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333
#include <linux/slab.h>
3434
#include <drm/drmP.h>
3535
#include <drm/amdgpu_drm.h>
36+
#include <drm/drm_cache.h>
3637
#include "amdgpu.h"
3738
#include "amdgpu_trace.h"
3839

@@ -261,6 +262,13 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
261262
AMDGPU_GEM_DOMAIN_OA);
262263

263264
bo->flags = flags;
265+
266+
/* For architectures that don't support WC memory,
267+
* mask out the WC flag from the BO
268+
*/
269+
if (!drm_arch_can_wc_memory())
270+
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
271+
264272
amdgpu_fill_placement_to_bo(bo, placement);
265273
/* Kernel allocation are uninterruptible */
266274
r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -808,7 +808,7 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
808808
flags |= AMDGPU_PTE_SNOOPED;
809809
}
810810

811-
if (adev->asic_type >= CHIP_TOPAZ)
811+
if (adev->asic_type >= CHIP_TONGA)
812812
flags |= AMDGPU_PTE_EXECUTABLE;
813813

814814
flags |= AMDGPU_PTE_READABLE;

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4738,6 +4738,22 @@ static int gfx_v7_0_early_init(void *handle)
47384738
return 0;
47394739
}
47404740

4741+
static int gfx_v7_0_late_init(void *handle)
4742+
{
4743+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4744+
int r;
4745+
4746+
r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4747+
if (r)
4748+
return r;
4749+
4750+
r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4751+
if (r)
4752+
return r;
4753+
4754+
return 0;
4755+
}
4756+
47414757
static int gfx_v7_0_sw_init(void *handle)
47424758
{
47434759
struct amdgpu_ring *ring;
@@ -4890,6 +4906,8 @@ static int gfx_v7_0_hw_fini(void *handle)
48904906
{
48914907
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
48924908

4909+
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4910+
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
48934911
gfx_v7_0_cp_enable(adev, false);
48944912
gfx_v7_0_rlc_stop(adev);
48954913
gfx_v7_0_fini_pg(adev);
@@ -5527,7 +5545,7 @@ static int gfx_v7_0_set_powergating_state(void *handle,
55275545

55285546
const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
55295547
.early_init = gfx_v7_0_early_init,
5530-
.late_init = NULL,
5548+
.late_init = gfx_v7_0_late_init,
55315549
.sw_init = gfx_v7_0_sw_init,
55325550
.sw_fini = gfx_v7_0_sw_fini,
55335551
.hw_init = gfx_v7_0_hw_init,

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Lines changed: 22 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,6 @@ MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
111111
MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
112112
MODULE_FIRMWARE("amdgpu/topaz_me.bin");
113113
MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
114-
MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
115114
MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
116115

117116
MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
@@ -828,7 +827,8 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
828827
adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
829828
adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
830829

831-
if (adev->asic_type != CHIP_STONEY) {
830+
if ((adev->asic_type != CHIP_STONEY) &&
831+
(adev->asic_type != CHIP_TOPAZ)) {
832832
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
833833
err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
834834
if (!err) {
@@ -3851,10 +3851,16 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
38513851
if (r)
38523852
return -EINVAL;
38533853

3854-
r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3855-
AMDGPU_UCODE_ID_CP_MEC1);
3856-
if (r)
3857-
return -EINVAL;
3854+
if (adev->asic_type == CHIP_TOPAZ) {
3855+
r = gfx_v8_0_cp_compute_load_microcode(adev);
3856+
if (r)
3857+
return r;
3858+
} else {
3859+
r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3860+
AMDGPU_UCODE_ID_CP_MEC1);
3861+
if (r)
3862+
return -EINVAL;
3863+
}
38583864
}
38593865
}
38603866

@@ -3901,6 +3907,8 @@ static int gfx_v8_0_hw_fini(void *handle)
39013907
{
39023908
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
39033909

3910+
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3911+
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
39043912
gfx_v8_0_cp_enable(adev, false);
39053913
gfx_v8_0_rlc_stop(adev);
39063914
gfx_v8_0_cp_compute_fini(adev);
@@ -4329,6 +4337,14 @@ static int gfx_v8_0_late_init(void *handle)
43294337
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
43304338
int r;
43314339

4340+
r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4341+
if (r)
4342+
return r;
4343+
4344+
r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4345+
if (r)
4346+
return r;
4347+
43324348
/* requires IBs so do in late init after IB pool is initialized */
43334349
r = gfx_v8_0_do_edc_gpr_workarounds(adev);
43344350
if (r)

‎drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

Lines changed: 41 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -42,9 +42,39 @@ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
4242

4343
MODULE_FIRMWARE("radeon/bonaire_mc.bin");
4444
MODULE_FIRMWARE("radeon/hawaii_mc.bin");
45+
MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46+
47+
static const u32 golden_settings_iceland_a11[] =
48+
{
49+
mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
50+
mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
51+
mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
52+
mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
53+
};
54+
55+
static const u32 iceland_mgcg_cgcg_init[] =
56+
{
57+
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
58+
};
59+
60+
static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
61+
{
62+
switch (adev->asic_type) {
63+
case CHIP_TOPAZ:
64+
amdgpu_program_register_sequence(adev,
65+
iceland_mgcg_cgcg_init,
66+
(const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
67+
amdgpu_program_register_sequence(adev,
68+
golden_settings_iceland_a11,
69+
(const u32)ARRAY_SIZE(golden_settings_iceland_a11));
70+
break;
71+
default:
72+
break;
73+
}
74+
}
4575

4676
/**
47-
* gmc8_mc_wait_for_idle - wait for MC idle callback.
77+
* gmc7_mc_wait_for_idle - wait for MC idle callback.
4878
*
4979
* @adev: amdgpu_device pointer
5080
*
@@ -132,13 +162,20 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
132162
case CHIP_HAWAII:
133163
chip_name = "hawaii";
134164
break;
165+
case CHIP_TOPAZ:
166+
chip_name = "topaz";
167+
break;
135168
case CHIP_KAVERI:
136169
case CHIP_KABINI:
137170
return 0;
138171
default: BUG();
139172
}
140173

141-
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
174+
if (adev->asic_type == CHIP_TOPAZ)
175+
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
176+
else
177+
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
178+
142179
err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
143180
if (err)
144181
goto out;
@@ -984,6 +1021,8 @@ static int gmc_v7_0_hw_init(void *handle)
9841021
int r;
9851022
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
9861023

1024+
gmc_v7_0_init_golden_registers(adev);
1025+
9871026
gmc_v7_0_mc_program(adev);
9881027

9891028
if (!(adev->flags & AMD_IS_APU)) {

‎drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

Lines changed: 1 addition & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -42,9 +42,7 @@
4242
static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
4343
static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
4444

45-
MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
4645
MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47-
MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
4846

4947
static const u32 golden_settings_tonga_a11[] =
5048
{
@@ -75,19 +73,6 @@ static const u32 fiji_mgcg_cgcg_init[] =
7573
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
7674
};
7775

78-
static const u32 golden_settings_iceland_a11[] =
79-
{
80-
mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
81-
mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
82-
mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83-
mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
84-
};
85-
86-
static const u32 iceland_mgcg_cgcg_init[] =
87-
{
88-
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
89-
};
90-
9176
static const u32 cz_mgcg_cgcg_init[] =
9277
{
9378
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
@@ -102,14 +87,6 @@ static const u32 stoney_mgcg_cgcg_init[] =
10287
static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
10388
{
10489
switch (adev->asic_type) {
105-
case CHIP_TOPAZ:
106-
amdgpu_program_register_sequence(adev,
107-
iceland_mgcg_cgcg_init,
108-
(const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
109-
amdgpu_program_register_sequence(adev,
110-
golden_settings_iceland_a11,
111-
(const u32)ARRAY_SIZE(golden_settings_iceland_a11));
112-
break;
11390
case CHIP_FIJI:
11491
amdgpu_program_register_sequence(adev,
11592
fiji_mgcg_cgcg_init,
@@ -229,15 +206,10 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
229206
DRM_DEBUG("\n");
230207

231208
switch (adev->asic_type) {
232-
case CHIP_TOPAZ:
233-
chip_name = "topaz";
234-
break;
235209
case CHIP_TONGA:
236210
chip_name = "tonga";
237211
break;
238212
case CHIP_FIJI:
239-
chip_name = "fiji";
240-
break;
241213
case CHIP_CARRIZO:
242214
case CHIP_STONEY:
243215
return 0;
@@ -1007,7 +979,7 @@ static int gmc_v8_0_hw_init(void *handle)
1007979

1008980
gmc_v8_0_mc_program(adev);
1009981

1010-
if (!(adev->flags & AMD_IS_APU)) {
982+
if (adev->asic_type == CHIP_TONGA) {
1011983
r = gmc_v8_0_mc_load_microcode(adev);
1012984
if (r) {
1013985
DRM_ERROR("Failed to load MC firmware!\n");

‎drivers/gpu/drm/amd/amdgpu/iceland_smc.c

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,7 @@ static uint32_t iceland_smu_get_mask_for_fw_type(uint32_t fw_type)
432432
case AMDGPU_UCODE_ID_CP_ME:
433433
return UCODE_ID_CP_ME_MASK;
434434
case AMDGPU_UCODE_ID_CP_MEC1:
435-
return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK;
435+
return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK;
436436
case AMDGPU_UCODE_ID_CP_MEC2:
437437
return UCODE_ID_CP_MEC_MASK;
438438
case AMDGPU_UCODE_ID_RLC_G:
@@ -522,12 +522,6 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
522522
return -EINVAL;
523523
}
524524

525-
if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
526-
&toc->entry[toc->num_entries++])) {
527-
DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
528-
return -EINVAL;
529-
}
530-
531525
if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
532526
&toc->entry[toc->num_entries++])) {
533527
DRM_ERROR("Failed to get firmware entry for SDMA0\n");
@@ -550,8 +544,8 @@ static int iceland_smu_request_load_fw(struct amdgpu_device *adev)
550544
UCODE_ID_CP_ME_MASK |
551545
UCODE_ID_CP_PFP_MASK |
552546
UCODE_ID_CP_MEC_MASK |
553-
UCODE_ID_CP_MEC_JT1_MASK |
554-
UCODE_ID_CP_MEC_JT2_MASK;
547+
UCODE_ID_CP_MEC_JT1_MASK;
548+
555549

556550
if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
557551
DRM_ERROR("Fail to request SMU load ucode\n");

‎drivers/gpu/drm/amd/amdgpu/vi.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@
6161
#include "vi.h"
6262
#include "vi_dpm.h"
6363
#include "gmc_v8_0.h"
64+
#include "gmc_v7_0.h"
6465
#include "gfx_v8_0.h"
6566
#include "sdma_v2_4.h"
6667
#include "sdma_v3_0.h"
@@ -1109,10 +1110,10 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
11091110
},
11101111
{
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.type = AMD_IP_BLOCK_TYPE_GMC,
1112-
.major = 8,
1113-
.minor = 0,
1113+
.major = 7,
1114+
.minor = 4,
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.rev = 0,
1115-
.funcs = &gmc_v8_0_ip_funcs,
1116+
.funcs = &gmc_v7_0_ip_funcs,
11161117
},
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{
11181119
.type = AMD_IP_BLOCK_TYPE_IH,
@@ -1442,8 +1443,7 @@ static int vi_common_early_init(void *handle)
14421443
break;
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case CHIP_FIJI:
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adev->has_uvd = true;
1445-
adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
1446-
AMDGPU_CG_SUPPORT_VCE_MGCG;
1446+
adev->cg_flags = 0;
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adev->pg_flags = 0;
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adev->external_rev_id = adev->rev_id + 0x3c;
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break;

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