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drm/sun4i: Add HDMI support
The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI controller. That HDMI controller is able to do audio and CEC, but those have been left out for now. Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
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‎drivers/gpu/drm/sun4i/Kconfig

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@@ -13,6 +13,14 @@ config DRM_SUN4I
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Display Engine. If M is selected the module will be called
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sun4i-drm.
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config DRM_SUN4I_HDMI
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tristate "Allwinner A10 HDMI Controller Support"
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depends on DRM_SUN4I
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default DRM_SUN4I
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help
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Choose this option if you have an Allwinner SoC with an HDMI
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controller.
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config DRM_SUN4I_BACKEND
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tristate "Support for Allwinner A10 Display Engine Backend"
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depends on DRM_SUN4I

‎drivers/gpu/drm/sun4i/Makefile

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@@ -1,6 +1,10 @@
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sun4i-drm-y += sun4i_drv.o
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sun4i-drm-y += sun4i_framebuffer.o
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sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
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sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o
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sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
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sun4i-tcon-y += sun4i_tcon.o
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sun4i-tcon-y += sun4i_rgb.o
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sun4i-tcon-y += sun4i_dotclock.o
@@ -15,4 +19,5 @@ obj-$(CONFIG_DRM_SUN4I) += sun6i_drc.o
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obj-$(CONFIG_DRM_SUN4I) += sun4i_tv.o
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obj-$(CONFIG_DRM_SUN4I_BACKEND) += sun4i-backend.o
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obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o
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obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o

‎drivers/gpu/drm/sun4i/sun4i_hdmi.h

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/*
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* Copyright (C) 2016 Maxime Ripard
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*
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* Maxime Ripard <[email protected]>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef _SUN4I_HDMI_H_
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#define _SUN4I_HDMI_H_
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#include <drm/drm_connector.h>
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#include <drm/drm_encoder.h>
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#define SUN4I_HDMI_CTRL_REG 0x004
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#define SUN4I_HDMI_CTRL_ENABLE BIT(31)
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#define SUN4I_HDMI_IRQ_REG 0x008
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#define SUN4I_HDMI_IRQ_STA_MASK 0x73
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#define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1)
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#define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
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#define SUN4I_HDMI_HPD_REG 0x00c
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#define SUN4I_HDMI_HPD_HIGH BIT(0)
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#define SUN4I_HDMI_VID_CTRL_REG 0x010
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#define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31)
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#define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30)
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#define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
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#define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
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#define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
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#define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020
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#define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))
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#define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)
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#define SUN4I_HDMI_VID_TIMING_POL_REG 0x024
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#define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16)
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#define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1)
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#define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0)
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#define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n))
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#define SUN4I_HDMI_PAD_CTRL0_REG 0x200
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#define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31)
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#define SUN4I_HDMI_PAD_CTRL0_LDOCEN BIT(30)
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#define SUN4I_HDMI_PAD_CTRL0_LDODEN BIT(29)
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#define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28)
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#define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27)
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#define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26)
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#define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25)
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#define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23)
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#define SUN4I_HDMI_PAD_CTRL1_REG 0x204
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#define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23)
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#define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22)
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#define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20)
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#define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19)
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#define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15)
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#define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14)
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#define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n) (((n) & 7) << 10)
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#define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6)
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#define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n) (((n) & 7) << 3)
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#define SUN4I_HDMI_PLL_CTRL_REG 0x208
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#define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31)
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#define SUN4I_HDMI_PLL_CTRL_BWS BIT(30)
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#define SUN4I_HDMI_PLL_CTRL_HV_IS_33 BIT(29)
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#define SUN4I_HDMI_PLL_CTRL_LDO1_EN BIT(28)
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#define SUN4I_HDMI_PLL_CTRL_LDO2_EN BIT(27)
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#define SUN4I_HDMI_PLL_CTRL_SDIV2 BIT(25)
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#define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n) (((n) & 7) << 20)
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#define SUN4I_HDMI_PLL_CTRL_S(n) (((n) & 7) << 17)
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#define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12)
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#define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8)
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#define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4)
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#define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4)
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#define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf)
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#define SUN4I_HDMI_PLL_DBG0_REG 0x20c
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#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21)
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#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21)
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#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21
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#define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n)))
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#define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4))
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#define SUN4I_HDMI_UNKNOWN_REG 0x300
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#define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27)
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#define SUN4I_HDMI_DDC_CTRL_REG 0x500
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#define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31)
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#define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30)
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#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8)
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#define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8)
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#define SUN4I_HDMI_DDC_CTRL_RESET BIT(0)
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#define SUN4I_HDMI_DDC_ADDR_REG 0x504
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#define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24)
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#define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
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#define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
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#define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff)
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#define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510
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#define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31)
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#define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518
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#define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c
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#define SUN4I_HDMI_DDC_CMD_REG 0x520
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#define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6
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#define SUN4I_HDMI_DDC_CLK_REG 0x528
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#define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3)
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#define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7)
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#define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540
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#define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE BIT(9)
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#define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE BIT(8)
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#define SUN4I_HDMI_DDC_FIFO_SIZE 16
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enum sun4i_hdmi_pkt_type {
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SUN4I_HDMI_PKT_AVI = 2,
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SUN4I_HDMI_PKT_END = 15,
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};
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struct sun4i_hdmi {
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struct drm_connector connector;
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struct drm_encoder encoder;
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struct device *dev;
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void __iomem *base;
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/* Parent clocks */
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struct clk *bus_clk;
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struct clk *mod_clk;
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struct clk *pll0_clk;
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struct clk *pll1_clk;
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/* And the clocks we create */
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struct clk *ddc_clk;
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struct clk *tmds_clk;
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struct sun4i_drv *drv;
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bool hdmi_monitor;
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};
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int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
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int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
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#endif /* _SUN4I_HDMI_H_ */

‎drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c

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/*
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* Copyright (C) 2016 Free Electrons
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* Copyright (C) 2016 NextThing Co
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*
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* Maxime Ripard <[email protected]>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "sun4i_tcon.h"
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#include "sun4i_hdmi.h"
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struct sun4i_ddc {
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struct clk_hw hw;
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struct sun4i_hdmi *hdmi;
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};
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static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
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{
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return container_of(hw, struct sun4i_ddc, hw);
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}
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static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
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unsigned long parent_rate,
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u8 *m, u8 *n)
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{
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unsigned long best_rate = 0;
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u8 best_m = 0, best_n = 0, _m, _n;
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for (_m = 0; _m < 8; _m++) {
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for (_n = 0; _n < 8; _n++) {
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unsigned long tmp_rate;
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tmp_rate = (((parent_rate / 2) / 10) >> _n) / (_m + 1);
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if (tmp_rate > rate)
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continue;
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if (abs(rate - tmp_rate) < abs(rate - best_rate)) {
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best_rate = tmp_rate;
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best_m = _m;
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best_n = _n;
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}
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}
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}
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if (m && n) {
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*m = best_m;
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*n = best_n;
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}
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return best_rate;
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}
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static long sun4i_ddc_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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return sun4i_ddc_calc_divider(rate, *prate, NULL, NULL);
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}
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static unsigned long sun4i_ddc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct sun4i_ddc *ddc = hw_to_ddc(hw);
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u32 reg;
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u8 m, n;
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reg = readl(ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
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m = (reg >> 3) & 0x7;
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n = reg & 0x7;
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return (((parent_rate / 2) / 10) >> n) / (m + 1);
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}
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static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct sun4i_ddc *ddc = hw_to_ddc(hw);
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u8 div_m, div_n;
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sun4i_ddc_calc_divider(rate, parent_rate, &div_m, &div_n);
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writel(SUN4I_HDMI_DDC_CLK_M(div_m) | SUN4I_HDMI_DDC_CLK_N(div_n),
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ddc->hdmi->base + SUN4I_HDMI_DDC_CLK_REG);
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return 0;
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}
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static const struct clk_ops sun4i_ddc_ops = {
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.recalc_rate = sun4i_ddc_recalc_rate,
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.round_rate = sun4i_ddc_round_rate,
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.set_rate = sun4i_ddc_set_rate,
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};
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int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
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{
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struct clk_init_data init;
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struct sun4i_ddc *ddc;
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const char *parent_name;
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parent_name = __clk_get_name(parent);
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if (!parent_name)
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return -ENODEV;
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ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
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if (!ddc)
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return -ENOMEM;
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init.name = "hdmi-ddc";
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init.ops = &sun4i_ddc_ops;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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ddc->hdmi = hdmi;
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ddc->hw.init = &init;
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hdmi->ddc_clk = devm_clk_register(hdmi->dev, &ddc->hw);
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if (IS_ERR(hdmi->ddc_clk))
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return PTR_ERR(hdmi->ddc_clk);
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return 0;
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}

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