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Merge tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "Updates for interrupt core and drivers: Core: - Fix a few inconsistencies between UP and SMP vs interrupt affinities - Small updates and cleanups all over the place New drivers: - LoongArch interrupt controller - Renesas RZ/G2L interrupt controller Updates: - Hotpath optimization for SiFive PLIC - Workaround for broken PLIC edge triggered interrupts - Simall cleanups and improvements as usual" * tag 'irq-core-2022-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (52 commits) irqchip/mmp: Declare init functions in common header file irqchip/mips-gic: Check the return value of ioremap() in gic_of_init() genirq: Use for_each_action_of_desc in actions_show() irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch irqchip: Add LoongArch CPU interrupt controller support irqchip: Add Loongson Extended I/O interrupt controller support irqchip/loongson-liointc: Add ACPI init support irqchip/loongson-pch-msi: Add ACPI init support irqchip/loongson-pch-pic: Add ACPI init support irqchip: Add Loongson PCH LPC controller support LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain LoongArch: Use ACPI_GENERIC_GSI for gsi handling genirq/generic_chip: Export irq_unmap_generic_chip ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback APCI: irq: Add support for multiple GSI domains LoongArch: Provisionally add ACPICA data structures irqdomain: Use hwirq_max instead of revmap_size for NOMAP domains irqdomain: Report irq number for NOMAP domains irqchip/gic-v3: Fix comment typo dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC ...
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‎Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,134 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
4+
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
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title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
8+
9+
maintainers:
10+
- Lad Prabhakar <[email protected]>
11+
- Geert Uytterhoeven <[email protected]>
12+
13+
description: |
14+
IA55 performs various interrupt controls including synchronization for the external
15+
interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
16+
interrupts output by each IP. And it notifies the interrupt to the GIC
17+
- IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
18+
- GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
19+
- NMI edge select (NMI is not treated as NMI exception and supports fall edge and
20+
stand-up edge detection interrupts)
21+
22+
allOf:
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- $ref: /schemas/interrupt-controller.yaml#
24+
25+
properties:
26+
compatible:
27+
items:
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- enum:
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- renesas,r9a07g044-irqc # RZ/G2{L,LC}
30+
- renesas,r9a07g054-irqc # RZ/V2L
31+
- const: renesas,rzg2l-irqc
32+
33+
'#interrupt-cells':
34+
description: The first cell should contain external interrupt number (IRQ0-7) and the
35+
second cell is used to specify the flag.
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const: 2
37+
38+
'#address-cells':
39+
const: 0
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41+
interrupt-controller: true
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reg:
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maxItems: 1
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interrupts:
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maxItems: 41
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: clk
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- const: pclk
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57+
power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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required:
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- compatible
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- '#interrupt-cells'
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- '#address-cells'
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- interrupt-controller
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- resets
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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82+
irqc: interrupt-controller@110a0000 {
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compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
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reg = <0x110a0000 0x10000>;
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
129+
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
130+
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
131+
clock-names = "clk", "pclk";
132+
power-domains = <&cpg>;
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resets = <&cpg R9A07G044_IA55_RESETN>;
134+
};

‎Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

Lines changed: 60 additions & 5 deletions
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@@ -26,9 +26,14 @@ description:
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with priority below this threshold will not cause the PLIC to raise its
2727
interrupt line leading to the context.
2828

29-
While the PLIC supports both edge-triggered and level-triggered interrupts,
30-
interrupt handlers are oblivious to this distinction and therefore it is not
31-
specified in the PLIC device-tree binding.
29+
The PLIC supports both edge-triggered and level-triggered interrupts. For
30+
edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31+
seen while an interrupt handler is active; the PLIC may either queue them or
32+
ignore them. In the first case, handlers are oblivious to the trigger type, so
33+
it is not included in the interrupt specifier. In the second case, software
34+
needs to know the trigger type, so it can reorder the interrupt flow to avoid
35+
missing interrupts. This special handling is needed by at least the Renesas
36+
RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
3237

3338
While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
3439
"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -47,6 +52,10 @@ maintainers:
4752
properties:
4853
compatible:
4954
oneOf:
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- items:
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- enum:
57+
- renesas,r9a07g043-plic
58+
- const: andestech,nceplic100
5059
- items:
5160
- enum:
5261
- sifive,fu540-c000-plic
@@ -64,8 +73,7 @@ properties:
6473
'#address-cells':
6574
const: 0
6675

67-
'#interrupt-cells':
68-
const: 1
76+
'#interrupt-cells': true
6977

7078
interrupt-controller: true
7179

@@ -82,6 +90,12 @@ properties:
8290
description:
8391
Specifies how many external interrupts are supported by this controller.
8492

93+
clocks: true
94+
95+
power-domains: true
96+
97+
resets: true
98+
8599
required:
86100
- compatible
87101
- '#address-cells'
@@ -91,6 +105,47 @@ required:
91105
- interrupts-extended
92106
- riscv,ndev
93107

108+
allOf:
109+
- if:
110+
properties:
111+
compatible:
112+
contains:
113+
enum:
114+
- andestech,nceplic100
115+
- thead,c900-plic
116+
117+
then:
118+
properties:
119+
'#interrupt-cells':
120+
const: 2
121+
122+
else:
123+
properties:
124+
'#interrupt-cells':
125+
const: 1
126+
127+
- if:
128+
properties:
129+
compatible:
130+
contains:
131+
const: renesas,r9a07g043-plic
132+
133+
then:
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properties:
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clocks:
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maxItems: 1
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138+
power-domains:
139+
maxItems: 1
140+
141+
resets:
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maxItems: 1
143+
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required:
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- clocks
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- power-domains
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- resets
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94149
additionalProperties: false
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96151
examples:

‎Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

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@@ -47,6 +47,17 @@ properties:
4747
gpio-ranges:
4848
maxItems: 1
4949

50+
interrupt-controller: true
51+
52+
'#interrupt-cells':
53+
const: 2
54+
description:
55+
The first cell contains the global GPIO port index, constructed using the
56+
RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
57+
second cell is used to specify the flag.
58+
E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
59+
being used as an interrupt.
60+
5061
clocks:
5162
maxItems: 1
5263

@@ -110,6 +121,8 @@ required:
110121
- gpio-controller
111122
- '#gpio-cells'
112123
- gpio-ranges
124+
- interrupt-controller
125+
- '#interrupt-cells'
113126
- clocks
114127
- power-domains
115128
- resets
@@ -126,6 +139,8 @@ examples:
126139
gpio-controller;
127140
#gpio-cells = <2>;
128141
gpio-ranges = <&pinctrl 0 0 392>;
142+
interrupt-controller;
143+
#interrupt-cells = <2>;
129144
clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
130145
resets = <&cpg R9A07G044_GPIO_RSTN>,
131146
<&cpg R9A07G044_GPIO_PORT_RESETN>,

‎arch/alpha/kernel/irq.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ int irq_select_affinity(unsigned int irq)
6060
cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
6161
last_cpu = cpu;
6262

63-
cpumask_copy(irq_data_get_affinity_mask(data), cpumask_of(cpu));
63+
irq_data_update_affinity(data, cpumask_of(cpu));
6464
chip->irq_set_affinity(data, cpumask_of(cpu), false);
6565
return 0;
6666
}

‎arch/arm/mach-hisi/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ config ARCH_HIP04
4040
select HAVE_ARM_ARCH_TIMER
4141
select MCPM if SMP
4242
select MCPM_QUAD_CLUSTER if SMP
43-
select GENERIC_IRQ_EFFECTIVE_AFF_MASK
43+
select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
4444
help
4545
Support for Hisilicon HiP04 SoC family
4646

‎arch/arm/mach-mmp/mmp2.h

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Original file line numberDiff line numberDiff line change
@@ -5,13 +5,13 @@
55
#include <linux/platform_data/pxa_sdhci.h>
66

77
extern void mmp2_timer_init(void);
8-
extern void __init mmp2_init_icu(void);
98
extern void __init mmp2_init_irq(void);
109
extern void mmp2_clear_pmic_int(void);
1110

1211
#include <linux/i2c.h>
1312
#include <linux/platform_data/i2c-pxa.h>
1413
#include <linux/platform_data/dma-mmp_tdma.h>
14+
#include <linux/irqchip/mmp.h>
1515

1616
#include "devices.h"
1717

‎arch/arm/mach-mmp/pxa168.h

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Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@
55
#include <linux/reboot.h>
66

77
extern void pxa168_timer_init(void);
8-
extern void __init icu_init_irq(void);
98
extern void __init pxa168_init_irq(void);
109
extern void pxa168_restart(enum reboot_mode, const char *);
1110
extern void pxa168_clear_keypad_wakeup(void);
@@ -18,6 +17,7 @@ extern void pxa168_clear_keypad_wakeup(void);
1817
#include <linux/pxa168_eth.h>
1918
#include <linux/platform_data/mv_usb.h>
2019
#include <linux/soc/mmp/cputype.h>
20+
#include <linux/irqchip/mmp.h>
2121

2222
#include "devices.h"
2323

‎arch/arm/mach-mmp/pxa910.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,13 +3,13 @@
33
#define __ASM_MACH_PXA910_H
44

55
extern void pxa910_timer_init(void);
6-
extern void __init icu_init_irq(void);
76
extern void __init pxa910_init_irq(void);
87

98
#include <linux/i2c.h>
109
#include <linux/platform_data/i2c-pxa.h>
1110
#include <linux/platform_data/mtd-nand-pxa3xx.h>
1211
#include <video/mmp_disp.h>
12+
#include <linux/irqchip/mmp.h>
1313

1414
#include "devices.h"
1515

‎arch/ia64/kernel/iosapic.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -834,7 +834,7 @@ iosapic_unregister_intr (unsigned int gsi)
834834
if (iosapic_intr_info[irq].count == 0) {
835835
#ifdef CONFIG_SMP
836836
/* Clear affinity */
837-
cpumask_setall(irq_get_affinity_mask(irq));
837+
irq_data_update_affinity(irq_get_irq_data(irq), cpu_all_mask);
838838
#endif
839839
/* Clear the interrupt information */
840840
iosapic_intr_info[irq].dest = 0;

‎arch/ia64/kernel/irq.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,8 @@ static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
5757
void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
5858
{
5959
if (irq < NR_IRQS) {
60-
cpumask_copy(irq_get_affinity_mask(irq),
61-
cpumask_of(cpu_logical_id(hwid)));
60+
irq_data_update_affinity(irq_get_irq_data(irq),
61+
cpumask_of(cpu_logical_id(hwid)));
6262
irq_redir[irq] = (char) (redir & 0xff);
6363
}
6464
}

‎arch/ia64/kernel/msi_ia64.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata,
3737
msg.data = data;
3838

3939
pci_write_msi_msg(irq, &msg);
40-
cpumask_copy(irq_data_get_affinity_mask(idata), cpumask_of(cpu));
40+
irq_data_update_affinity(idata, cpumask_of(cpu));
4141

4242
return 0;
4343
}
@@ -132,7 +132,7 @@ static int dmar_msi_set_affinity(struct irq_data *data,
132132
msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu));
133133

134134
dmar_msi_write(irq, &msg);
135-
cpumask_copy(irq_data_get_affinity_mask(data), mask);
135+
irq_data_update_affinity(data, mask);
136136

137137
return 0;
138138
}

‎arch/loongarch/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
config LOONGARCH
33
bool
44
default y
5+
select ACPI_GENERIC_GSI if ACPI
56
select ACPI_SYSTEM_POWER_STATES_SUPPORT if ACPI
67
select ARCH_BINFMT_ELF_STATE
78
select ARCH_ENABLE_MEMORY_HOTPLUG

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