mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS

The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.

Signed-off-by: Sergei Shtylyov <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Fixes: 2a68ea7 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC")
Cc: [email protected] # v4.14+
Signed-off-by: Ulf Hansson <[email protected]>

Author: Sergei Shtylyov

drivers/mmc/host/renesas_sdhi_internal_dmac.c

@@ -45,7 +45,7 @@
 /* DM_CM_RST */
 #define RST_DTRANRST1		BIT(9)
 #define RST_DTRANRST0		BIT(8)
-#define RST_RESERVED_BITS	GENMASK_ULL(32, 0)
+#define RST_RESERVED_BITS	GENMASK_ULL(31, 0)
 
 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
 #define INFO1_CLEAR		0