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rushil-googlevijay-suman
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gve: Control path for DQO-QPL
GVE supports QPL ("queue-page-list") mode where all data is communicated through a set of pre-registered pages. Adding this mode to DQO descriptor format. Add checks, abi-changes and device options to support QPL mode for DQO in addition to GQI. Also, use pages-per-qpl supplied by device-option to control the size of the "queue-page-list". Signed-off-by: Rushil Gupta <[email protected]> Reviewed-by: Willem de Bruijn <[email protected]> Signed-off-by: Praveen Kaligineedi <[email protected]> Signed-off-by: Bailey Forrest <[email protected]> Signed-off-by: David S. Miller <[email protected]> (cherry picked from commit 66ce8e6) Orabug: 37356729 Signed-off-by: Yifei Liu <[email protected]> Reviewed-by: Saeed Mirzamohammadi <[email protected]> Conflicts: drivers/net/ethernet/google/gve/gve_main.c code base different due to missing some upstream commits. Apply the changes Signed-off-by: Saeed Mirzamohammadi <[email protected]> Signed-off-by: Vijayendra Suman <[email protected]>
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4 files changed

+128
-18
lines changed

4 files changed

+128
-18
lines changed

drivers/net/ethernet/google/gve/gve.h

Lines changed: 26 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,12 @@
4949

5050
#define GVE_GQ_TX_MIN_PKT_DESC_BYTES 182
5151

52+
#define DQO_QPL_DEFAULT_TX_PAGES 512
53+
#define DQO_QPL_DEFAULT_RX_PAGES 2048
54+
55+
/* Maximum TSO size supported on DQO */
56+
#define GVE_DQO_TX_MAX 0x3FFFF
57+
5258
/* Each slot in the desc ring has a 1:1 mapping to a slot in the data ring */
5359
struct gve_rx_desc_queue {
5460
struct gve_rx_desc *desc_ring; /* the descriptor ring */
@@ -215,6 +221,9 @@ struct gve_rx_ring {
215221
* which cannot be reused yet.
216222
*/
217223
struct gve_index_list used_buf_states;
224+
225+
/* qpl assigned to this queue */
226+
struct gve_queue_page_list *qpl;
218227
} dqo;
219228
};
220229

@@ -433,6 +442,12 @@ struct gve_tx_ring {
433442
s16 num_pending_packets;
434443

435444
u32 complq_mask; /* complq size is complq_mask + 1 */
445+
446+
/* QPL fields */
447+
struct {
448+
/* qpl assigned to this queue */
449+
struct gve_queue_page_list *qpl;
450+
};
436451
} dqo;
437452
} ____cacheline_aligned;
438453
struct netdev_queue *netdev_txq;
@@ -505,6 +520,7 @@ enum gve_queue_format {
505520
GVE_GQI_RDA_FORMAT = 0x1,
506521
GVE_GQI_QPL_FORMAT = 0x2,
507522
GVE_DQO_RDA_FORMAT = 0x3,
523+
GVE_DQO_QPL_FORMAT = 0x4,
508524
};
509525

510526
struct gve_priv {
@@ -524,7 +540,8 @@ struct gve_priv {
524540
u16 num_event_counters;
525541
u16 tx_desc_cnt; /* num desc per ring */
526542
u16 rx_desc_cnt; /* num desc per ring */
527-
u16 tx_pages_per_qpl; /* tx buffer length */
543+
u16 tx_pages_per_qpl; /* Suggested number of pages per qpl for TX queues by NIC */
544+
u16 rx_pages_per_qpl; /* Suggested number of pages per qpl for RX queues by NIC */
528545
u16 rx_data_slot_cnt; /* rx buffer length */
529546
u64 max_registered_pages;
530547
u64 num_registered_pages; /* num pages registered with NIC */
@@ -780,11 +797,17 @@ static inline u32 gve_rx_idx_to_ntfy(struct gve_priv *priv, u32 queue_idx)
780797
return (priv->num_ntfy_blks / 2) + queue_idx;
781798
}
782799

800+
static inline bool gve_is_qpl(struct gve_priv *priv)
801+
{
802+
return priv->queue_format == GVE_GQI_QPL_FORMAT ||
803+
priv->queue_format == GVE_DQO_QPL_FORMAT;
804+
}
805+
783806
/* Returns the number of tx queue page lists
784807
*/
785808
static inline u32 gve_num_tx_qpls(struct gve_priv *priv)
786809
{
787-
if (priv->queue_format != GVE_GQI_QPL_FORMAT)
810+
if (!gve_is_qpl(priv))
788811
return 0;
789812

790813
return priv->tx_cfg.num_queues;
@@ -794,7 +817,7 @@ static inline u32 gve_num_tx_qpls(struct gve_priv *priv)
794817
*/
795818
static inline u32 gve_num_rx_qpls(struct gve_priv *priv)
796819
{
797-
if (priv->queue_format != GVE_GQI_QPL_FORMAT)
820+
if (!gve_is_qpl(priv))
798821
return 0;
799822

800823
return priv->rx_cfg.num_queues;

drivers/net/ethernet/google/gve/gve_adminq.c

Lines changed: 78 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,8 @@ void gve_parse_device_option(struct gve_priv *priv,
3939
struct gve_device_option_gqi_rda **dev_op_gqi_rda,
4040
struct gve_device_option_gqi_qpl **dev_op_gqi_qpl,
4141
struct gve_device_option_dqo_rda **dev_op_dqo_rda,
42-
struct gve_device_option_jumbo_frames **dev_op_jumbo_frames)
42+
struct gve_device_option_jumbo_frames **dev_op_jumbo_frames,
43+
struct gve_device_option_dqo_qpl **dev_op_dqo_qpl)
4344
{
4445
u32 req_feat_mask = be32_to_cpu(option->required_features_mask);
4546
u16 option_length = be16_to_cpu(option->option_length);
@@ -112,6 +113,22 @@ void gve_parse_device_option(struct gve_priv *priv,
112113
}
113114
*dev_op_dqo_rda = (void *)(option + 1);
114115
break;
116+
case GVE_DEV_OPT_ID_DQO_QPL:
117+
if (option_length < sizeof(**dev_op_dqo_qpl) ||
118+
req_feat_mask != GVE_DEV_OPT_REQ_FEAT_MASK_DQO_QPL) {
119+
dev_warn(&priv->pdev->dev, GVE_DEVICE_OPTION_ERROR_FMT,
120+
"DQO QPL", (int)sizeof(**dev_op_dqo_qpl),
121+
GVE_DEV_OPT_REQ_FEAT_MASK_DQO_QPL,
122+
option_length, req_feat_mask);
123+
break;
124+
}
125+
126+
if (option_length > sizeof(**dev_op_dqo_qpl)) {
127+
dev_warn(&priv->pdev->dev,
128+
GVE_DEVICE_OPTION_TOO_BIG_FMT, "DQO QPL");
129+
}
130+
*dev_op_dqo_qpl = (void *)(option + 1);
131+
break;
115132
case GVE_DEV_OPT_ID_JUMBO_FRAMES:
116133
if (option_length < sizeof(**dev_op_jumbo_frames) ||
117134
req_feat_mask != GVE_DEV_OPT_REQ_FEAT_MASK_JUMBO_FRAMES) {
@@ -146,7 +163,8 @@ gve_process_device_options(struct gve_priv *priv,
146163
struct gve_device_option_gqi_rda **dev_op_gqi_rda,
147164
struct gve_device_option_gqi_qpl **dev_op_gqi_qpl,
148165
struct gve_device_option_dqo_rda **dev_op_dqo_rda,
149-
struct gve_device_option_jumbo_frames **dev_op_jumbo_frames)
166+
struct gve_device_option_jumbo_frames **dev_op_jumbo_frames,
167+
struct gve_device_option_dqo_qpl **dev_op_dqo_qpl)
150168
{
151169
const int num_options = be16_to_cpu(descriptor->num_device_options);
152170
struct gve_device_option *dev_opt;
@@ -166,7 +184,8 @@ gve_process_device_options(struct gve_priv *priv,
166184

167185
gve_parse_device_option(priv, descriptor, dev_opt,
168186
dev_op_gqi_rda, dev_op_gqi_qpl,
169-
dev_op_dqo_rda, dev_op_jumbo_frames);
187+
dev_op_dqo_rda, dev_op_jumbo_frames,
188+
dev_op_dqo_qpl);
170189
dev_opt = next_opt;
171190
}
172191

@@ -505,12 +524,24 @@ static int gve_adminq_create_tx_queue(struct gve_priv *priv, u32 queue_index)
505524

506525
cmd.create_tx_queue.queue_page_list_id = cpu_to_be32(qpl_id);
507526
} else {
527+
u16 comp_ring_size;
528+
u32 qpl_id = 0;
529+
530+
if (priv->queue_format == GVE_DQO_RDA_FORMAT) {
531+
qpl_id = GVE_RAW_ADDRESSING_QPL_ID;
532+
comp_ring_size =
533+
priv->options_dqo_rda.tx_comp_ring_entries;
534+
} else {
535+
qpl_id = tx->dqo.qpl->id;
536+
comp_ring_size = priv->tx_desc_cnt;
537+
}
538+
cmd.create_tx_queue.queue_page_list_id = cpu_to_be32(qpl_id);
508539
cmd.create_tx_queue.tx_ring_size =
509540
cpu_to_be16(priv->tx_desc_cnt);
510541
cmd.create_tx_queue.tx_comp_ring_addr =
511542
cpu_to_be64(tx->complq_bus_dqo);
512543
cmd.create_tx_queue.tx_comp_ring_size =
513-
cpu_to_be16(priv->options_dqo_rda.tx_comp_ring_entries);
544+
cpu_to_be16(comp_ring_size);
514545
}
515546

516547
return gve_adminq_issue_cmd(priv, &cmd);
@@ -555,6 +586,18 @@ static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index)
555586
cmd.create_rx_queue.queue_page_list_id = cpu_to_be32(qpl_id);
556587
cmd.create_rx_queue.packet_buffer_size = cpu_to_be16(rx->packet_buffer_size);
557588
} else {
589+
u16 rx_buff_ring_entries;
590+
u32 qpl_id = 0;
591+
592+
if (priv->queue_format == GVE_DQO_RDA_FORMAT) {
593+
qpl_id = GVE_RAW_ADDRESSING_QPL_ID;
594+
rx_buff_ring_entries =
595+
priv->options_dqo_rda.rx_buff_ring_entries;
596+
} else {
597+
qpl_id = rx->dqo.qpl->id;
598+
rx_buff_ring_entries = priv->rx_desc_cnt;
599+
}
600+
cmd.create_rx_queue.queue_page_list_id = cpu_to_be32(qpl_id);
558601
cmd.create_rx_queue.rx_ring_size =
559602
cpu_to_be16(priv->rx_desc_cnt);
560603
cmd.create_rx_queue.rx_desc_ring_addr =
@@ -564,7 +607,7 @@ static int gve_adminq_create_rx_queue(struct gve_priv *priv, u32 queue_index)
564607
cmd.create_rx_queue.packet_buffer_size =
565608
cpu_to_be16(priv->data_buffer_size_dqo);
566609
cmd.create_rx_queue.rx_buff_ring_size =
567-
cpu_to_be16(priv->options_dqo_rda.rx_buff_ring_entries);
610+
cpu_to_be16(rx_buff_ring_entries);
568611
cmd.create_rx_queue.enable_rsc =
569612
!!(priv->dev->features & NETIF_F_LRO);
570613
}
@@ -675,9 +718,13 @@ gve_set_desc_cnt_dqo(struct gve_priv *priv,
675718
const struct gve_device_option_dqo_rda *dev_op_dqo_rda)
676719
{
677720
priv->tx_desc_cnt = be16_to_cpu(descriptor->tx_queue_entries);
721+
priv->rx_desc_cnt = be16_to_cpu(descriptor->rx_queue_entries);
722+
723+
if (priv->queue_format == GVE_DQO_QPL_FORMAT)
724+
return 0;
725+
678726
priv->options_dqo_rda.tx_comp_ring_entries =
679727
be16_to_cpu(dev_op_dqo_rda->tx_comp_ring_entries);
680-
priv->rx_desc_cnt = be16_to_cpu(descriptor->rx_queue_entries);
681728
priv->options_dqo_rda.rx_buff_ring_entries =
682729
be16_to_cpu(dev_op_dqo_rda->rx_buff_ring_entries);
683730

@@ -687,7 +734,9 @@ gve_set_desc_cnt_dqo(struct gve_priv *priv,
687734
static void gve_enable_supported_features(struct gve_priv *priv,
688735
u32 supported_features_mask,
689736
const struct gve_device_option_jumbo_frames
690-
*dev_op_jumbo_frames)
737+
*dev_op_jumbo_frames,
738+
const struct gve_device_option_dqo_qpl
739+
*dev_op_dqo_qpl)
691740
{
692741
/* Before control reaches this point, the page-size-capped max MTU from
693742
* the gve_device_descriptor field has already been stored in
@@ -699,6 +748,18 @@ static void gve_enable_supported_features(struct gve_priv *priv,
699748
"JUMBO FRAMES device option enabled.\n");
700749
priv->dev->max_mtu = be16_to_cpu(dev_op_jumbo_frames->max_mtu);
701750
}
751+
752+
/* Override pages for qpl for DQO-QPL */
753+
if (dev_op_dqo_qpl) {
754+
priv->tx_pages_per_qpl =
755+
be16_to_cpu(dev_op_dqo_qpl->tx_pages_per_qpl);
756+
priv->rx_pages_per_qpl =
757+
be16_to_cpu(dev_op_dqo_qpl->rx_pages_per_qpl);
758+
if (priv->tx_pages_per_qpl == 0)
759+
priv->tx_pages_per_qpl = DQO_QPL_DEFAULT_TX_PAGES;
760+
if (priv->rx_pages_per_qpl == 0)
761+
priv->rx_pages_per_qpl = DQO_QPL_DEFAULT_RX_PAGES;
762+
}
702763
}
703764

704765
int gve_adminq_describe_device(struct gve_priv *priv)
@@ -707,6 +768,7 @@ int gve_adminq_describe_device(struct gve_priv *priv)
707768
struct gve_device_option_gqi_rda *dev_op_gqi_rda = NULL;
708769
struct gve_device_option_gqi_qpl *dev_op_gqi_qpl = NULL;
709770
struct gve_device_option_dqo_rda *dev_op_dqo_rda = NULL;
771+
struct gve_device_option_dqo_qpl *dev_op_dqo_qpl = NULL;
710772
struct gve_device_descriptor *descriptor;
711773
u32 supported_features_mask = 0;
712774
union gve_adminq_command cmd;
@@ -733,21 +795,26 @@ int gve_adminq_describe_device(struct gve_priv *priv)
733795

734796
err = gve_process_device_options(priv, descriptor, &dev_op_gqi_rda,
735797
&dev_op_gqi_qpl, &dev_op_dqo_rda,
736-
&dev_op_jumbo_frames);
798+
&dev_op_jumbo_frames,
799+
&dev_op_dqo_qpl);
737800
if (err)
738801
goto free_device_descriptor;
739802

740803
/* If the GQI_RAW_ADDRESSING option is not enabled and the queue format
741804
* is not set to GqiRda, choose the queue format in a priority order:
742-
* DqoRda, GqiRda, GqiQpl. Use GqiQpl as default.
805+
* DqoRda, DqoQpl, GqiRda, GqiQpl. Use GqiQpl as default.
743806
*/
744807
if (dev_op_dqo_rda) {
745808
priv->queue_format = GVE_DQO_RDA_FORMAT;
746809
dev_info(&priv->pdev->dev,
747810
"Driver is running with DQO RDA queue format.\n");
748811
supported_features_mask =
749812
be32_to_cpu(dev_op_dqo_rda->supported_features_mask);
750-
} else if (dev_op_gqi_rda) {
813+
} else if (dev_op_dqo_qpl) {
814+
priv->queue_format = GVE_DQO_QPL_FORMAT;
815+
supported_features_mask =
816+
be32_to_cpu(dev_op_dqo_qpl->supported_features_mask);
817+
} else if (dev_op_gqi_rda) {
751818
priv->queue_format = GVE_GQI_RDA_FORMAT;
752819
dev_info(&priv->pdev->dev,
753820
"Driver is running with GQI RDA queue format.\n");
@@ -798,7 +865,7 @@ int gve_adminq_describe_device(struct gve_priv *priv)
798865
priv->default_num_queues = be16_to_cpu(descriptor->default_num_queues);
799866

800867
gve_enable_supported_features(priv, supported_features_mask,
801-
dev_op_jumbo_frames);
868+
dev_op_jumbo_frames, dev_op_dqo_qpl);
802869

803870
free_device_descriptor:
804871
dma_free_coherent(&priv->pdev->dev, PAGE_SIZE, descriptor,

drivers/net/ethernet/google/gve/gve_adminq.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,14 @@ struct gve_device_option_dqo_rda {
109109

110110
static_assert(sizeof(struct gve_device_option_dqo_rda) == 8);
111111

112+
struct gve_device_option_dqo_qpl {
113+
__be32 supported_features_mask;
114+
__be16 tx_pages_per_qpl;
115+
__be16 rx_pages_per_qpl;
116+
};
117+
118+
static_assert(sizeof(struct gve_device_option_dqo_qpl) == 8);
119+
112120
struct gve_device_option_jumbo_frames {
113121
__be32 supported_features_mask;
114122
__be16 max_mtu;
@@ -130,6 +138,7 @@ enum gve_dev_opt_id {
130138
GVE_DEV_OPT_ID_GQI_RDA = 0x2,
131139
GVE_DEV_OPT_ID_GQI_QPL = 0x3,
132140
GVE_DEV_OPT_ID_DQO_RDA = 0x4,
141+
GVE_DEV_OPT_ID_DQO_QPL = 0x7,
133142
GVE_DEV_OPT_ID_JUMBO_FRAMES = 0x8,
134143
};
135144

@@ -139,6 +148,7 @@ enum gve_dev_opt_req_feat_mask {
139148
GVE_DEV_OPT_REQ_FEAT_MASK_GQI_QPL = 0x0,
140149
GVE_DEV_OPT_REQ_FEAT_MASK_DQO_RDA = 0x0,
141150
GVE_DEV_OPT_REQ_FEAT_MASK_JUMBO_FRAMES = 0x0,
151+
GVE_DEV_OPT_REQ_FEAT_MASK_DQO_QPL = 0x0,
142152
};
143153

144154
enum gve_sup_feature_mask {

drivers/net/ethernet/google/gve/gve_main.c

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -489,7 +489,7 @@ static int gve_setup_device_resources(struct gve_priv *priv)
489489
goto abort_with_stats_report;
490490
}
491491

492-
if (priv->queue_format == GVE_DQO_RDA_FORMAT) {
492+
if (!gve_is_gqi(priv)) {
493493
priv->ptype_lut_dqo = kvzalloc(sizeof(*priv->ptype_lut_dqo),
494494
GFP_KERNEL);
495495
if (!priv->ptype_lut_dqo) {
@@ -892,25 +892,35 @@ static void gve_free_queue_page_list(struct gve_priv *priv, u32 id)
892892
static int gve_alloc_qpls(struct gve_priv *priv)
893893
{
894894
int num_qpls = gve_num_tx_qpls(priv) + gve_num_rx_qpls(priv);
895+
int page_count;
895896
int i, j;
896897
int err;
897898

898-
if (num_qpls == 0)
899+
/* Raw addressing means no QPLs */
900+
if (!gve_is_qpl(priv))
899901
return 0;
900902

901903
priv->qpls = kvcalloc(num_qpls, sizeof(*priv->qpls), GFP_KERNEL);
902904
if (!priv->qpls)
903905
return -ENOMEM;
904906

907+
page_count = priv->tx_pages_per_qpl;
905908
for (i = 0; i < gve_num_tx_qpls(priv); i++) {
906909
err = gve_alloc_queue_page_list(priv, i,
907-
priv->tx_pages_per_qpl);
910+
page_count);
908911
if (err)
909912
goto free_qpls;
910913
}
914+
915+
/* For GQI_QPL number of pages allocated have 1:1 relationship with
916+
* number of descriptors. For DQO, number of pages required are
917+
* more than descriptors (because of out of order completions).
918+
*/
919+
page_count = priv->queue_format == GVE_GQI_QPL_FORMAT ?
920+
priv->rx_data_slot_cnt : priv->rx_pages_per_qpl;
911921
for (; i < num_qpls; i++) {
912922
err = gve_alloc_queue_page_list(priv, i,
913-
priv->rx_data_slot_cnt);
923+
page_count);
914924
if (err)
915925
goto free_qpls;
916926
}

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