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npigginmpe
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powerpc/64s: Fix dt_cpu_ftrs to have restore_cpu clear unwanted LPCR bits
Presently the dt_cpu_ftrs restore_cpu will only add bits to the LPCR for secondaries, but some bits must be removed (e.g., UPRT for HPT). Not clearing these bits on secondaries causes checkstops when booting with disable_radix. restore_cpu can not just set LPCR, because it is also called by the idle wakeup code which relies on opal_slw_set_reg to restore the value of LPCR, at least on P8 which does not save LPCR to stack in the idle code. Fix this by including a mask of bits to clear from LPCR as well, which is used by restore_cpu. This is a little messy now, but it's a minimal fix that can be backported. Longer term, the idle SPR save/restore code can be reworked to completely avoid calls to restore_cpu, then restore_cpu would be able to unconditionally set LPCR to match boot processor environment. Fixes: 5a61ef7 ("powerpc/64s: Support new device tree binding for discovering CPU features") Cc: [email protected] # v4.12+ Signed-off-by: Nicholas Piggin <[email protected]> Signed-off-by: Michael Ellerman <[email protected]>
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arch/powerpc/kernel/dt_cpu_ftrs.c

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,7 @@ static int hv_mode;
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static struct {
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u64 lpcr;
86+
u64 lpcr_clear;
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u64 hfscr;
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u64 fscr;
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} system_registers;
@@ -91,6 +92,8 @@ static void (*init_pmu_registers)(void);
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static void __restore_cpu_cpufeatures(void)
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{
95+
u64 lpcr;
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/*
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* LPCR is restored by the power on engine already. It can be changed
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* after early init e.g., by radix enable, and we have no unified API
@@ -103,8 +106,10 @@ static void __restore_cpu_cpufeatures(void)
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* The best we can do to accommodate secondary boot and idle restore
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* for now is "or" LPCR with existing.
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*/
106-
107-
mtspr(SPRN_LPCR, system_registers.lpcr | mfspr(SPRN_LPCR));
109+
lpcr = mfspr(SPRN_LPCR);
110+
lpcr |= system_registers.lpcr;
111+
lpcr &= ~system_registers.lpcr_clear;
112+
mtspr(SPRN_LPCR, lpcr);
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if (hv_mode) {
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mtspr(SPRN_LPID, 0);
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mtspr(SPRN_HFSCR, system_registers.hfscr);
@@ -324,8 +329,9 @@ static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
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{
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u64 lpcr;
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332+
system_registers.lpcr_clear |= (LPCR_ISL | LPCR_UPRT | LPCR_HR);
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lpcr = mfspr(SPRN_LPCR);
328-
lpcr &= ~LPCR_ISL;
334+
lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR);
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mtspr(SPRN_LPCR, lpcr);
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cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;

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