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/* Filter configuration */
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#define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
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- DFSDM_CR1_RSYNC_MASK)
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+ DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
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+ DFSDM_CR1_JSCAN_MASK)
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enum sd_converter_type {
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DFSDM_AUDIO ,
@@ -58,6 +59,8 @@ struct stm32_dfsdm_adc {
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struct stm32_dfsdm * dfsdm ;
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const struct stm32_dfsdm_dev_data * dev_data ;
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unsigned int fl_id ;
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+ unsigned int nconv ;
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+ unsigned long smask ;
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/* ADC specific */
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unsigned int oversamp ;
@@ -204,19 +207,39 @@ static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl,
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return 0 ;
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}
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- static int stm32_dfsdm_start_channel (struct stm32_dfsdm * dfsdm ,
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- unsigned int ch_id )
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+ static int stm32_dfsdm_start_channel (struct stm32_dfsdm_adc * adc )
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{
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- return regmap_update_bits (dfsdm -> regmap , DFSDM_CHCFGR1 (ch_id ),
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- DFSDM_CHCFGR1_CHEN_MASK ,
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- DFSDM_CHCFGR1_CHEN (1 ));
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+ struct iio_dev * indio_dev = iio_priv_to_dev (adc );
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+ struct regmap * regmap = adc -> dfsdm -> regmap ;
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+ const struct iio_chan_spec * chan ;
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+ unsigned int bit ;
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+ int ret ;
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+
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+ for_each_set_bit (bit , & adc -> smask , sizeof (adc -> smask ) * BITS_PER_BYTE ) {
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+ chan = indio_dev -> channels + bit ;
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+ ret = regmap_update_bits (regmap , DFSDM_CHCFGR1 (chan -> channel ),
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+ DFSDM_CHCFGR1_CHEN_MASK ,
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+ DFSDM_CHCFGR1_CHEN (1 ));
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+ if (ret < 0 )
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+ return ret ;
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+ }
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+
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+ return 0 ;
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}
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- static void stm32_dfsdm_stop_channel (struct stm32_dfsdm * dfsdm ,
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- unsigned int ch_id )
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+ static void stm32_dfsdm_stop_channel (struct stm32_dfsdm_adc * adc )
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{
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- regmap_update_bits (dfsdm -> regmap , DFSDM_CHCFGR1 (ch_id ),
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- DFSDM_CHCFGR1_CHEN_MASK , DFSDM_CHCFGR1_CHEN (0 ));
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+ struct iio_dev * indio_dev = iio_priv_to_dev (adc );
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+ struct regmap * regmap = adc -> dfsdm -> regmap ;
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+ const struct iio_chan_spec * chan ;
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+ unsigned int bit ;
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+
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+ for_each_set_bit (bit , & adc -> smask , sizeof (adc -> smask ) * BITS_PER_BYTE ) {
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+ chan = indio_dev -> channels + bit ;
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+ regmap_update_bits (regmap , DFSDM_CHCFGR1 (chan -> channel ),
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+ DFSDM_CHCFGR1_CHEN_MASK ,
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+ DFSDM_CHCFGR1_CHEN (0 ));
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+ }
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}
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static int stm32_dfsdm_chan_configure (struct stm32_dfsdm * dfsdm ,
@@ -241,9 +264,10 @@ static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
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DFSDM_CHCFGR1_CHINSEL (ch -> alt_si ));
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}
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- static int stm32_dfsdm_start_filter (struct stm32_dfsdm * dfsdm ,
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+ static int stm32_dfsdm_start_filter (struct stm32_dfsdm_adc * adc ,
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unsigned int fl_id )
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{
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+ struct stm32_dfsdm * dfsdm = adc -> dfsdm ;
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int ret ;
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/* Enable filter */
@@ -252,7 +276,11 @@ static int stm32_dfsdm_start_filter(struct stm32_dfsdm *dfsdm,
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if (ret < 0 )
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return ret ;
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- /* Start conversion */
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+ /* Nothing more to do for injected (scan mode/triggered) conversions */
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+ if (adc -> nconv > 1 )
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+ return 0 ;
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+
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+ /* Software start (single or continuous) regular conversion */
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return regmap_update_bits (dfsdm -> regmap , DFSDM_CR1 (fl_id ),
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DFSDM_CR1_RSWSTART_MASK ,
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DFSDM_CR1_RSWSTART (1 ));
@@ -267,12 +295,14 @@ static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
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}
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static int stm32_dfsdm_filter_configure (struct stm32_dfsdm_adc * adc ,
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- unsigned int fl_id , unsigned int ch_id )
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+ unsigned int fl_id )
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{
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struct iio_dev * indio_dev = iio_priv_to_dev (adc );
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struct regmap * regmap = adc -> dfsdm -> regmap ;
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struct stm32_dfsdm_filter * fl = & adc -> dfsdm -> fl_list [fl_id ];
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u32 cr1 ;
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+ const struct iio_chan_spec * chan ;
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+ unsigned int bit , jchg = 0 ;
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int ret ;
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/* Average integrator oversampling */
@@ -292,14 +322,59 @@ static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc,
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if (ret )
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return ret ;
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- /* No scan mode supported for the moment */
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- cr1 = DFSDM_CR1_RCH (ch_id );
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+ /*
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+ * DFSDM modes configuration W.R.T audio/iio type modes
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+ * ----------------------------------------------------------------
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+ * Modes | regular | regular | injected | injected |
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+ * | | continuous | | + scan |
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+ * --------------|---------|--------------|----------|------------|
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+ * single conv | x | | | |
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+ * (1 chan) | | | | |
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+ * --------------|---------|--------------|----------|------------|
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+ * 1 Audio chan | | sample freq | | |
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+ * | | or sync_mode | | |
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+ * --------------|---------|--------------|----------|------------|
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+ * 1 IIO chan | | sample freq | trigger | |
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+ * | | or sync_mode | | |
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+ * --------------|---------|--------------|----------|------------|
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+ * 2+ IIO chans | | | | trigger or |
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+ * | | | | sync_mode |
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+ * ----------------------------------------------------------------
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+ */
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+ if (adc -> nconv == 1 ) {
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+ bit = __ffs (adc -> smask );
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+ chan = indio_dev -> channels + bit ;
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- /* Continuous conversions triggered by SPI clock in buffer mode */
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- if (indio_dev -> currentmode & INDIO_BUFFER_SOFTWARE )
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- cr1 |= DFSDM_CR1_RCONT (1 );
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+ /* Use regular conversion for single channel without trigger */
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+ cr1 = DFSDM_CR1_RCH (chan -> channel );
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- cr1 |= DFSDM_CR1_RSYNC (fl -> sync_mode );
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+ /* Continuous conversions triggered by SPI clk in buffer mode */
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+ if (indio_dev -> currentmode & INDIO_BUFFER_SOFTWARE )
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+ cr1 |= DFSDM_CR1_RCONT (1 );
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+
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+ cr1 |= DFSDM_CR1_RSYNC (fl -> sync_mode );
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+ } else {
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+ /* Use injected conversion for multiple channels */
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+ for_each_set_bit (bit , & adc -> smask ,
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+ sizeof (adc -> smask ) * BITS_PER_BYTE ) {
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+ chan = indio_dev -> channels + bit ;
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+ jchg |= BIT (chan -> channel );
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+ }
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+ ret = regmap_write (regmap , DFSDM_JCHGR (fl_id ), jchg );
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+ if (ret < 0 )
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+ return ret ;
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+
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+ /* Use scan mode for multiple channels */
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+ cr1 = DFSDM_CR1_JSCAN (1 );
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+
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+ /*
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+ * Continuous conversions not supported in injected mode:
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+ * - use conversions in sync with filter 0
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+ */
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+ if (!fl -> sync_mode )
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+ return - EINVAL ;
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+ cr1 |= DFSDM_CR1_JSYNC (fl -> sync_mode );
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+ }
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return regmap_update_bits (regmap , DFSDM_CR1 (fl_id ), DFSDM_CR1_CFG_MASK ,
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cr1 );
@@ -428,21 +503,20 @@ static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
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return len ;
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}
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- static int stm32_dfsdm_start_conv (struct stm32_dfsdm_adc * adc ,
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- const struct iio_chan_spec * chan )
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+ static int stm32_dfsdm_start_conv (struct stm32_dfsdm_adc * adc )
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{
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struct regmap * regmap = adc -> dfsdm -> regmap ;
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int ret ;
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- ret = stm32_dfsdm_start_channel (adc -> dfsdm , chan -> channel );
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+ ret = stm32_dfsdm_start_channel (adc );
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if (ret < 0 )
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return ret ;
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- ret = stm32_dfsdm_filter_configure (adc , adc -> fl_id , chan -> channel );
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+ ret = stm32_dfsdm_filter_configure (adc , adc -> fl_id );
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if (ret < 0 )
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goto stop_channels ;
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- ret = stm32_dfsdm_start_filter (adc -> dfsdm , adc -> fl_id );
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+ ret = stm32_dfsdm_start_filter (adc , adc -> fl_id );
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if (ret < 0 )
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goto filter_unconfigure ;
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@@ -452,13 +526,12 @@ static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
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regmap_update_bits (regmap , DFSDM_CR1 (adc -> fl_id ),
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DFSDM_CR1_CFG_MASK , 0 );
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stop_channels :
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- stm32_dfsdm_stop_channel (adc -> dfsdm , chan -> channel );
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+ stm32_dfsdm_stop_channel (adc );
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return ret ;
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}
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- static void stm32_dfsdm_stop_conv (struct stm32_dfsdm_adc * adc ,
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- const struct iio_chan_spec * chan )
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+ static void stm32_dfsdm_stop_conv (struct stm32_dfsdm_adc * adc )
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{
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struct regmap * regmap = adc -> dfsdm -> regmap ;
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@@ -467,7 +540,7 @@ static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc,
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regmap_update_bits (regmap , DFSDM_CR1 (adc -> fl_id ),
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DFSDM_CR1_CFG_MASK , 0 );
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- stm32_dfsdm_stop_channel (adc -> dfsdm , chan -> channel );
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+ stm32_dfsdm_stop_channel (adc );
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}
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static int stm32_dfsdm_set_watermark (struct iio_dev * indio_dev ,
@@ -557,8 +630,7 @@ static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
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{
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struct stm32_dfsdm_adc * adc = iio_priv (indio_dev );
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struct dma_slave_config config = {
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- .src_addr = (dma_addr_t )adc -> dfsdm -> phys_base +
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- DFSDM_RDATAR (adc -> fl_id ),
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+ .src_addr = (dma_addr_t )adc -> dfsdm -> phys_base ,
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.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES ,
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};
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struct dma_async_tx_descriptor * desc ;
@@ -571,6 +643,10 @@ static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
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dev_dbg (& indio_dev -> dev , "%s size=%d watermark=%d\n" , __func__ ,
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adc -> buf_sz , adc -> buf_sz / 2 );
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+ if (adc -> nconv == 1 )
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+ config .src_addr += DFSDM_RDATAR (adc -> fl_id );
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+ else
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+ config .src_addr += DFSDM_JDATAR (adc -> fl_id );
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ret = dmaengine_slave_config (adc -> dma_chan , & config );
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if (ret )
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return ret ;
@@ -595,9 +671,20 @@ static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
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/* Issue pending DMA requests */
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dma_async_issue_pending (adc -> dma_chan );
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- /* Enable DMA transfer*/
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- ret = regmap_update_bits (adc -> dfsdm -> regmap , DFSDM_CR1 (adc -> fl_id ),
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- DFSDM_CR1_RDMAEN_MASK , DFSDM_CR1_RDMAEN_MASK );
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+ if (adc -> nconv == 1 ) {
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+ /* Enable regular DMA transfer*/
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+ ret = regmap_update_bits (adc -> dfsdm -> regmap ,
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+ DFSDM_CR1 (adc -> fl_id ),
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+ DFSDM_CR1_RDMAEN_MASK ,
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+ DFSDM_CR1_RDMAEN_MASK );
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+ } else {
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+ /* Enable injected DMA transfer*/
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+ ret = regmap_update_bits (adc -> dfsdm -> regmap ,
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+ DFSDM_CR1 (adc -> fl_id ),
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+ DFSDM_CR1_JDMAEN_MASK ,
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+ DFSDM_CR1_JDMAEN_MASK );
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+ }
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+
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if (ret < 0 )
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goto err_stop_dma ;
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@@ -617,14 +704,26 @@ static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
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return ;
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regmap_update_bits (adc -> dfsdm -> regmap , DFSDM_CR1 (adc -> fl_id ),
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- DFSDM_CR1_RDMAEN_MASK , 0 );
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+ DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK , 0 );
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dmaengine_terminate_all (adc -> dma_chan );
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}
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+ static int stm32_dfsdm_update_scan_mode (struct iio_dev * indio_dev ,
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+ const unsigned long * scan_mask )
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+ {
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+ struct stm32_dfsdm_adc * adc = iio_priv (indio_dev );
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+
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+ adc -> nconv = bitmap_weight (scan_mask , indio_dev -> masklength );
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+ adc -> smask = * scan_mask ;
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+
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+ dev_dbg (& indio_dev -> dev , "nconv=%d mask=%lx\n" , adc -> nconv , * scan_mask );
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+
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+ return 0 ;
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+ }
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+
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static int stm32_dfsdm_postenable (struct iio_dev * indio_dev )
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{
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struct stm32_dfsdm_adc * adc = iio_priv (indio_dev );
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- const struct iio_chan_spec * chan = & indio_dev -> channels [0 ];
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int ret ;
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/* Reset adc buffer index */
@@ -646,7 +745,7 @@ static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
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goto stop_dfsdm ;
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}
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- ret = stm32_dfsdm_start_conv (adc , chan );
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+ ret = stm32_dfsdm_start_conv (adc );
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if (ret ) {
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dev_err (& indio_dev -> dev , "Can't start conversion\n" );
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goto err_stop_dma ;
@@ -668,9 +767,8 @@ static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
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static int stm32_dfsdm_predisable (struct iio_dev * indio_dev )
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{
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struct stm32_dfsdm_adc * adc = iio_priv (indio_dev );
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- const struct iio_chan_spec * chan = & indio_dev -> channels [0 ];
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- stm32_dfsdm_stop_conv (adc , chan );
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+ stm32_dfsdm_stop_conv (adc );
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stm32_dfsdm_adc_dma_stop (indio_dev );
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@@ -756,7 +854,9 @@ static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
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if (ret < 0 )
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goto stop_dfsdm ;
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- ret = stm32_dfsdm_start_conv (adc , chan );
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+ adc -> nconv = 1 ;
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+ adc -> smask = BIT (chan -> scan_index );
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+ ret = stm32_dfsdm_start_conv (adc );
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if (ret < 0 ) {
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regmap_update_bits (adc -> dfsdm -> regmap , DFSDM_CR2 (adc -> fl_id ),
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DFSDM_CR2_REOCIE_MASK , DFSDM_CR2_REOCIE (0 ));
@@ -777,7 +877,7 @@ static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
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else
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ret = IIO_VAL_INT ;
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- stm32_dfsdm_stop_conv (adc , chan );
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+ stm32_dfsdm_stop_conv (adc );
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stop_dfsdm :
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stm32_dfsdm_stop_dfsdm (adc -> dfsdm );
@@ -882,11 +982,13 @@ static const struct iio_info stm32_dfsdm_info_audio = {
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.hwfifo_set_watermark = stm32_dfsdm_set_watermark ,
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.read_raw = stm32_dfsdm_read_raw ,
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.write_raw = stm32_dfsdm_write_raw ,
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+ .update_scan_mode = stm32_dfsdm_update_scan_mode ,
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};
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static const struct iio_info stm32_dfsdm_info_adc = {
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.read_raw = stm32_dfsdm_read_raw ,
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.write_raw = stm32_dfsdm_write_raw ,
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+ .update_scan_mode = stm32_dfsdm_update_scan_mode ,
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};
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static irqreturn_t stm32_dfsdm_irq (int irq , void * arg )
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