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TE-N-ShengjiuWangabelvesa
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dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support
Add the clock dt-binding file for Audio Clock Mux. which is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL. Add the clockid for clocks in header file. The Audio Clock Mux is binded with all the audio IP and audio clocks in the subsystem, so need to list the power domain of related clocks and IPs. Each clock and IP has a power domain, so there are so many power domains. Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
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‎Documentation/devicetree/bindings/clock/fsl,imx8-acm.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8 Audio Clock Mux
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maintainers:
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- Shengjiu Wang <[email protected]>
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description: |
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NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
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used to control Audio related clock on the SoC.
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properties:
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compatible:
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enum:
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- fsl,imx8dxl-acm
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- fsl,imx8qm-acm
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- fsl,imx8qxp-acm
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reg:
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maxItems: 1
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power-domains:
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minItems: 13
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maxItems: 21
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'#clock-cells':
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const: 1
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description:
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
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for the full list of i.MX8 ACM clock IDs.
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clocks:
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minItems: 13
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maxItems: 27
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clock-names:
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minItems: 13
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maxItems: 27
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required:
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- compatible
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- reg
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- power-domains
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- '#clock-cells'
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qxp-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 18
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maxItems: 18
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_ASRC_1
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- description: power domain of IMX_SC_R_ESAI_0
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- description: power domain of IMX_SC_R_ESAI_1
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SAI_4
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- description: power domain of IMX_SC_R_SAI_5
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- description: power domain of IMX_SC_R_SAI_6
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- description: power domain of IMX_SC_R_SAI_7
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_SPDIF_1
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 27
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maxItems: 27
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: mlb_clk
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- const: hdmi_rx_mclk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: esai0_rx_clk
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- const: esai0_rx_hf_clk
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- const: esai0_tx_clk
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- const: esai0_tx_hf_clk
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- const: esai1_rx_clk
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- const: esai1_rx_hf_clk
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- const: esai1_tx_clk
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- const: esai1_tx_hf_clk
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- const: spdif0_rx
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- const: spdif1_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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- const: sai4_rx_bclk
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- const: sai5_tx_bclk
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- const: sai6_rx_bclk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8dxl-acm
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then:
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properties:
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power-domains:
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items:
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- description: power domain of IMX_SC_R_AUDIO_CLK_0
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- description: power domain of IMX_SC_R_AUDIO_CLK_1
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- description: power domain of IMX_SC_R_MCLK_OUT_0
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- description: power domain of IMX_SC_R_MCLK_OUT_1
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- description: power domain of IMX_SC_R_AUDIO_PLL_0
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- description: power domain of IMX_SC_R_AUDIO_PLL_1
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- description: power domain of IMX_SC_R_ASRC_0
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- description: power domain of IMX_SC_R_SAI_0
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- description: power domain of IMX_SC_R_SAI_1
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- description: power domain of IMX_SC_R_SAI_2
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- description: power domain of IMX_SC_R_SAI_3
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- description: power domain of IMX_SC_R_SPDIF_0
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- description: power domain of IMX_SC_R_MQS_0
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clocks:
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minItems: 13
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maxItems: 13
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clock-names:
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items:
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- const: aud_rec_clk0_lpcg_clk
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- const: aud_rec_clk1_lpcg_clk
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- const: aud_pll_div_clk0_lpcg_clk
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- const: aud_pll_div_clk1_lpcg_clk
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- const: ext_aud_mclk0
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- const: ext_aud_mclk1
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- const: spdif0_rx
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- const: sai0_rx_bclk
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- const: sai0_tx_bclk
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- const: sai1_rx_bclk
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- const: sai1_tx_bclk
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- const: sai2_rx_bclk
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- const: sai3_rx_bclk
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additionalProperties: false
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examples:
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# Clock Control Module node:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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clock-controller@59e00000 {
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compatible = "fsl,imx8qxp-acm";
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reg = <0x59e00000 0x1d0000>;
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#clock-cells = <1>;
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power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
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<&pd IMX_SC_R_AUDIO_CLK_1>,
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<&pd IMX_SC_R_MCLK_OUT_0>,
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<&pd IMX_SC_R_MCLK_OUT_1>,
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<&pd IMX_SC_R_AUDIO_PLL_0>,
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<&pd IMX_SC_R_AUDIO_PLL_1>,
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<&pd IMX_SC_R_ASRC_0>,
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<&pd IMX_SC_R_ASRC_1>,
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<&pd IMX_SC_R_ESAI_0>,
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<&pd IMX_SC_R_SAI_0>,
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<&pd IMX_SC_R_SAI_1>,
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<&pd IMX_SC_R_SAI_2>,
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<&pd IMX_SC_R_SAI_3>,
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<&pd IMX_SC_R_SAI_4>,
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<&pd IMX_SC_R_SAI_5>,
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<&pd IMX_SC_R_SPDIF_0>,
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<&pd IMX_SC_R_MQS_0>;
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clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
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<&aud_rec1_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
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<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
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<&clk_ext_aud_mclk0>,
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<&clk_ext_aud_mclk1>,
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<&clk_esai0_rx_clk>,
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<&clk_esai0_rx_hf_clk>,
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<&clk_esai0_tx_clk>,
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<&clk_esai0_tx_hf_clk>,
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<&clk_spdif0_rx>,
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<&clk_sai0_rx_bclk>,
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<&clk_sai0_tx_bclk>,
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<&clk_sai1_rx_bclk>,
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<&clk_sai1_tx_bclk>,
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<&clk_sai2_rx_bclk>,
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<&clk_sai3_rx_bclk>,
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<&clk_sai4_rx_bclk>;
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clock-names = "aud_rec_clk0_lpcg_clk",
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"aud_rec_clk1_lpcg_clk",
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"aud_pll_div_clk0_lpcg_clk",
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"aud_pll_div_clk1_lpcg_clk",
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"ext_aud_mclk0",
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"ext_aud_mclk1",
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"esai0_rx_clk",
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"esai0_rx_hf_clk",
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"esai0_tx_clk",
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"esai0_tx_hf_clk",
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"spdif0_rx",
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"sai0_rx_bclk",
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"sai0_tx_bclk",
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"sai1_rx_bclk",
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"sai1_tx_bclk",
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"sai2_rx_bclk",
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"sai3_rx_bclk",
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"sai4_rx_bclk";
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};

‎include/dt-bindings/clock/imx8-clock.h

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#define IMX_ADMA_LPCG_CLK_END 45
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#define IMX_ADMA_ACM_AUD_CLK0_SEL 0
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#define IMX_ADMA_ACM_AUD_CLK1_SEL 1
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#define IMX_ADMA_ACM_MCLKOUT0_SEL 2
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#define IMX_ADMA_ACM_MCLKOUT1_SEL 3
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#define IMX_ADMA_ACM_ESAI0_MCLK_SEL 4
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#define IMX_ADMA_ACM_ESAI1_MCLK_SEL 5
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#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 6
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#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 7
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#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 8
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#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 9
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#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 10
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#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 11
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#define IMX_ADMA_ACM_SAI0_MCLK_SEL 12
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#define IMX_ADMA_ACM_SAI1_MCLK_SEL 13
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#define IMX_ADMA_ACM_SAI2_MCLK_SEL 14
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#define IMX_ADMA_ACM_SAI3_MCLK_SEL 15
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#define IMX_ADMA_ACM_SAI4_MCLK_SEL 16
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#define IMX_ADMA_ACM_SAI5_MCLK_SEL 17
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#define IMX_ADMA_ACM_SAI6_MCLK_SEL 18
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#define IMX_ADMA_ACM_SAI7_MCLK_SEL 19
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#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 20
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#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 21
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#define IMX_ADMA_ACM_MQS_TX_CLK_SEL 22
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#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 23
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#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 24
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#define IMX_ADMA_ACM_CLK_END 25
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#endif /* __DT_BINDINGS_CLOCK_IMX_H */

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