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33 | 33 | #define TBCTL 0x00
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34 | 34 | #define TBPRD 0x0A
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35 | 35 |
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36 |
| -#define TBCTL_RUN_MASK (BIT(15) | BIT(14)) |
37 |
| -#define TBCTL_STOP_NEXT 0 |
38 |
| -#define TBCTL_STOP_ON_CYCLE BIT(14) |
39 |
| -#define TBCTL_FREE_RUN (BIT(15) | BIT(14)) |
40 | 36 | #define TBCTL_PRDLD_MASK BIT(3)
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41 | 37 | #define TBCTL_PRDLD_SHDW 0
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42 | 38 | #define TBCTL_PRDLD_IMDT BIT(3)
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@@ -360,17 +356,14 @@ static int ehrpwm_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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360 | 356 | /* Channels polarity can be configured from action qualifier module */
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361 | 357 | configure_polarity(pc, pwm->hwpwm);
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362 | 358 |
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363 |
| - /* Enable TBCLK before enabling PWM device */ |
| 359 | + /* Enable TBCLK */ |
364 | 360 | ret = clk_enable(pc->tbclk);
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365 | 361 | if (ret) {
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366 | 362 | dev_err(chip->dev, "Failed to enable TBCLK for %s: %d\n",
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367 | 363 | dev_name(pc->chip.dev), ret);
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368 | 364 | return ret;
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369 | 365 | }
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370 | 366 |
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371 |
| - /* Enable time counter for free_run */ |
372 |
| - ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_FREE_RUN); |
373 |
| - |
374 | 367 | return 0;
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375 | 368 | }
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376 | 369 |
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@@ -400,9 +393,6 @@ static void ehrpwm_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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400 | 393 | /* Disabling TBCLK on PWM disable */
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401 | 394 | clk_disable(pc->tbclk);
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402 | 395 |
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403 |
| - /* Stop Time base counter */ |
404 |
| - ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_RUN_MASK, TBCTL_STOP_NEXT); |
405 |
| - |
406 | 396 | /* Disable clock on PWM disable */
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407 | 397 | pm_runtime_put_sync(chip->dev);
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408 | 398 | }
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