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62 | 62 | #define FLEXCAN_MCR_BCC BIT(16)
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63 | 63 | #define FLEXCAN_MCR_LPRIO_EN BIT(13)
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64 | 64 | #define FLEXCAN_MCR_AEN BIT(12)
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65 |
| -#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f) |
| 65 | +#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) |
66 | 66 | #define FLEXCAN_MCR_IDAM_A (0 << 8)
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67 | 67 | #define FLEXCAN_MCR_IDAM_B (1 << 8)
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68 | 68 | #define FLEXCAN_MCR_IDAM_C (2 << 8)
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125 | 125 | FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
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126 | 126 |
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127 | 127 | /* FLEXCAN interrupt flag register (IFLAG) bits */
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128 |
| -#define FLEXCAN_TX_BUF_ID 8 |
| 128 | +/* Errata ERR005829 step7: Reserve first valid MB */ |
| 129 | +#define FLEXCAN_TX_BUF_RESERVED 8 |
| 130 | +#define FLEXCAN_TX_BUF_ID 9 |
129 | 131 | #define FLEXCAN_IFLAG_BUF(x) BIT(x)
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130 | 132 | #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
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131 | 133 | #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
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136 | 138 |
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137 | 139 | /* FLEXCAN message buffers */
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138 | 140 | #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
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| 141 | +#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) |
| 142 | +#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) |
| 143 | +#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) |
| 144 | +#define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24) |
| 145 | +#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) |
| 146 | + |
| 147 | +#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) |
| 148 | +#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) |
| 149 | +#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) |
| 150 | +#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) |
| 151 | + |
139 | 152 | #define FLEXCAN_MB_CNT_SRR BIT(22)
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140 | 153 | #define FLEXCAN_MB_CNT_IDE BIT(21)
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141 | 154 | #define FLEXCAN_MB_CNT_RTR BIT(20)
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@@ -428,6 +441,14 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
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428 | 441 | flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
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429 | 442 | flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
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430 | 443 |
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| 444 | + /* Errata ERR005829 step8: |
| 445 | + * Write twice INACTIVE(0x8) code to first MB. |
| 446 | + */ |
| 447 | + flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, |
| 448 | + ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); |
| 449 | + flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, |
| 450 | + ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); |
| 451 | + |
431 | 452 | return NETDEV_TX_OK;
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432 | 453 | }
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433 | 454 |
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@@ -744,6 +765,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
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744 | 765 | stats->tx_bytes += can_get_echo_skb(dev, 0);
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745 | 766 | stats->tx_packets++;
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746 | 767 | can_led_event(dev, CAN_LED_EVENT_TX);
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| 768 | + /* after sending a RTR frame mailbox is in RX mode */ |
| 769 | + flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, |
| 770 | + ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl); |
747 | 771 | flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
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748 | 772 | netif_wake_queue(dev);
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749 | 773 | }
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@@ -801,6 +825,7 @@ static int flexcan_chip_start(struct net_device *dev)
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801 | 825 | struct flexcan_regs __iomem *regs = priv->base;
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802 | 826 | int err;
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803 | 827 | u32 reg_mcr, reg_ctrl;
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| 828 | + int i; |
804 | 829 |
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805 | 830 | /* enable module */
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806 | 831 | err = flexcan_chip_enable(priv);
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@@ -867,8 +892,18 @@ static int flexcan_chip_start(struct net_device *dev)
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867 | 892 | netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
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868 | 893 | flexcan_write(reg_ctrl, ®s->ctrl);
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869 | 894 |
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870 |
| - /* Abort any pending TX, mark Mailbox as INACTIVE */ |
871 |
| - flexcan_write(FLEXCAN_MB_CNT_CODE(0x4), |
| 895 | + /* clear and invalidate all mailboxes first */ |
| 896 | + for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) { |
| 897 | + flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE, |
| 898 | + ®s->cantxfg[i].can_ctrl); |
| 899 | + } |
| 900 | + |
| 901 | + /* Errata ERR005829: mark first TX mailbox as INACTIVE */ |
| 902 | + flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, |
| 903 | + ®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl); |
| 904 | + |
| 905 | + /* mark TX mailbox as INACTIVE */ |
| 906 | + flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE, |
872 | 907 | ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
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873 | 908 |
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874 | 909 | /* acceptance mask/acceptance code (accept everything) */
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