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John Garryacmel
John Garry
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acmel
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perf vendor events arm64: fixup A53 to use recommended events
This patch fixes the ARM Cortex-A53 json to use event definition from the ARMv8 recommended events. In addition to this change, other changes were made: - remove stray ',' - remove mirrored events in memory.json and bus.json - fixed indentation to be consistent with other ARM JSONs Signed-off-by: John Garry <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Andi Kleen <[email protected]> Cc: Ganapatrao Kulkarni <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Shaokun Zhang <[email protected]> Cc: Will Deacon <[email protected]> Cc: William Cohen <[email protected]> Cc: [email protected] Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
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-92
lines changed

6 files changed

+62
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‎tools/perf/pmu-events/arch/arm64/arm/cortex-a53/branch.json

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,23 @@
11
[
2-
{,
3-
"EventCode": "0x7A",
4-
"EventName": "BR_INDIRECT_SPEC",
5-
"BriefDescription": "Branch speculatively executed - Indirect branch"
2+
{
3+
"ArchStdEvent": "BR_INDIRECT_SPEC",
64
},
7-
{,
5+
{
86
"EventCode": "0xC9",
97
"EventName": "BR_COND",
108
"BriefDescription": "Conditional branch executed"
119
},
12-
{,
10+
{
1311
"EventCode": "0xCA",
1412
"EventName": "BR_INDIRECT_MISPRED",
1513
"BriefDescription": "Indirect branch mispredicted"
1614
},
17-
{,
15+
{
1816
"EventCode": "0xCB",
1917
"EventName": "BR_INDIRECT_MISPRED_ADDR",
2018
"BriefDescription": "Indirect branch mispredicted because of address miscompare"
2119
},
22-
{,
20+
{
2321
"EventCode": "0xCC",
2422
"EventName": "BR_COND_MISPRED",
2523
"BriefDescription": "Conditional branch mispredicted"

‎tools/perf/pmu-events/arch/arm64/arm/cortex-a53/bus.json

Lines changed: 4 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,8 @@
11
[
2-
{,
3-
"EventCode": "0x60",
4-
"EventName": "BUS_ACCESS_LD",
5-
"BriefDescription": "Bus access - Read"
2+
{
3+
"ArchStdEvent": "BUS_ACCESS_RD",
64
},
7-
{,
8-
"EventCode": "0x61",
9-
"EventName": "BUS_ACCESS_ST",
10-
"BriefDescription": "Bus access - Write"
11-
},
12-
{,
13-
"EventCode": "0xC0",
14-
"EventName": "EXT_MEM_REQ",
15-
"BriefDescription": "External memory request"
16-
},
17-
{,
18-
"EventCode": "0xC1",
19-
"EventName": "EXT_MEM_REQ_NC",
20-
"BriefDescription": "Non-cacheable external memory request"
5+
{
6+
"ArchStdEvent": "BUS_ACCESS_WR",
217
}
228
]

‎tools/perf/pmu-events/arch/arm64/arm/cortex-a53/cache.json

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,27 @@
11
[
2-
{,
3-
"EventCode": "0xC2",
4-
"EventName": "PREFETCH_LINEFILL",
5-
"BriefDescription": "Linefill because of prefetch"
2+
{
3+
"EventCode": "0xC2",
4+
"EventName": "PREFETCH_LINEFILL",
5+
"BriefDescription": "Linefill because of prefetch"
66
},
7-
{,
8-
"EventCode": "0xC3",
9-
"EventName": "PREFETCH_LINEFILL_DROP",
10-
"BriefDescription": "Instruction Cache Throttle occurred"
7+
{
8+
"EventCode": "0xC3",
9+
"EventName": "PREFETCH_LINEFILL_DROP",
10+
"BriefDescription": "Instruction Cache Throttle occurred"
1111
},
12-
{,
13-
"EventCode": "0xC4",
14-
"EventName": "READ_ALLOC_ENTER",
15-
"BriefDescription": "Entering read allocate mode"
12+
{
13+
"EventCode": "0xC4",
14+
"EventName": "READ_ALLOC_ENTER",
15+
"BriefDescription": "Entering read allocate mode"
1616
},
17-
{,
18-
"EventCode": "0xC5",
19-
"EventName": "READ_ALLOC",
20-
"BriefDescription": "Read allocate mode"
17+
{
18+
"EventCode": "0xC5",
19+
"EventName": "READ_ALLOC",
20+
"BriefDescription": "Read allocate mode"
2121
},
22-
{,
23-
"EventCode": "0xC8",
24-
"EventName": "EXT_SNOOP",
25-
"BriefDescription": "SCU Snooped data from another CPU for this CPU"
22+
{
23+
"EventCode": "0xC8",
24+
"EventName": "EXT_SNOOP",
25+
"BriefDescription": "SCU Snooped data from another CPU for this CPU"
2626
}
2727
]

‎tools/perf/pmu-events/arch/arm64/arm/cortex-a53/memory.json

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,10 @@
11
[
2-
{,
3-
"EventCode": "0x60",
4-
"EventName": "BUS_ACCESS_LD",
5-
"BriefDescription": "Bus access - Read"
6-
},
7-
{,
8-
"EventCode": "0x61",
9-
"EventName": "BUS_ACCESS_ST",
10-
"BriefDescription": "Bus access - Write"
11-
},
12-
{,
2+
{
133
"EventCode": "0xC0",
144
"EventName": "EXT_MEM_REQ",
155
"BriefDescription": "External memory request"
166
},
17-
{,
7+
{
188
"EventCode": "0xC1",
199
"EventName": "EXT_MEM_REQ_NC",
2010
"BriefDescription": "Non-cacheable external memory request"

‎tools/perf/pmu-events/arch/arm64/arm/cortex-a53/other.json

Lines changed: 20 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,32 +1,28 @@
11
[
2-
{,
3-
"EventCode": "0x86",
4-
"EventName": "EXC_IRQ",
5-
"BriefDescription": "Exception taken, IRQ"
2+
{
3+
"ArchStdEvent": "EXC_IRQ",
64
},
7-
{,
8-
"EventCode": "0x87",
9-
"EventName": "EXC_FIQ",
10-
"BriefDescription": "Exception taken, FIQ"
5+
{
6+
"ArchStdEvent": "EXC_FIQ",
117
},
12-
{,
13-
"EventCode": "0xC6",
14-
"EventName": "PRE_DECODE_ERR",
15-
"BriefDescription": "Pre-decode error"
8+
{
9+
"EventCode": "0xC6",
10+
"EventName": "PRE_DECODE_ERR",
11+
"BriefDescription": "Pre-decode error"
1612
},
17-
{,
18-
"EventCode": "0xD0",
19-
"EventName": "L1I_CACHE_ERR",
20-
"BriefDescription": "L1 Instruction Cache (data or tag) memory error"
13+
{
14+
"EventCode": "0xD0",
15+
"EventName": "L1I_CACHE_ERR",
16+
"BriefDescription": "L1 Instruction Cache (data or tag) memory error"
2117
},
22-
{,
23-
"EventCode": "0xD1",
24-
"EventName": "L1D_CACHE_ERR",
25-
"BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
18+
{
19+
"EventCode": "0xD1",
20+
"EventName": "L1D_CACHE_ERR",
21+
"BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
2622
},
27-
{,
28-
"EventCode": "0xD2",
29-
"EventName": "TLB_ERR",
30-
"BriefDescription": "TLB memory error"
23+
{
24+
"EventCode": "0xD2",
25+
"EventName": "TLB_ERR",
26+
"BriefDescription": "TLB memory error"
3127
}
3228
]

‎tools/perf/pmu-events/arch/arm64/arm/cortex-a53/pipeline.json

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,50 +1,50 @@
11
[
2-
{,
2+
{
33
"EventCode": "0xC7",
44
"EventName": "STALL_SB_FULL",
55
"BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
66
},
7-
{,
7+
{
88
"EventCode": "0xE0",
99
"EventName": "OTHER_IQ_DEP_STALL",
1010
"BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
1111
},
12-
{,
12+
{
1313
"EventCode": "0xE1",
1414
"EventName": "IC_DEP_STALL",
1515
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
1616
},
17-
{,
17+
{
1818
"EventCode": "0xE2",
1919
"EventName": "IUTLB_DEP_STALL",
2020
"BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
2121
},
22-
{,
22+
{
2323
"EventCode": "0xE3",
2424
"EventName": "DECODE_DEP_STALL",
2525
"BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
2626
},
27-
{,
27+
{
2828
"EventCode": "0xE4",
2929
"EventName": "OTHER_INTERLOCK_STALL",
3030
"BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
3131
},
32-
{,
32+
{
3333
"EventCode": "0xE5",
3434
"EventName": "AGU_DEP_STALL",
3535
"BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
3636
},
37-
{,
37+
{
3838
"EventCode": "0xE6",
3939
"EventName": "SIMD_DEP_STALL",
4040
"BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
4141
},
42-
{,
42+
{
4343
"EventCode": "0xE7",
4444
"EventName": "LD_DEP_STALL",
4545
"BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
4646
},
47-
{,
47+
{
4848
"EventCode": "0xE8",
4949
"EventName": "ST_DEP_STALL",
5050
"BriefDescription": "Cycles there is a stall in the Wr stage because of a store"

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