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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
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‎Documentation/devicetree/bindings/arm/atmel-at91.txt

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ System Timer (ST) required properties:
5252
- reg: Should contain registers location and length
5353
- interrupts: Should contain interrupt for the ST which is the IRQ line
5454
shared across all System Controller members.
55+
- clocks: phandle to input clock.
5556
Its subnodes can be:
5657
- watchdog: compatible should be "atmel,at91rm9200-wdt"
5758

@@ -63,7 +64,7 @@ TC/TCLIB Timer required properties:
6364
Note that you can specify several interrupt cells if the TC
6465
block has one interrupt per channel.
6566
- clock-names: tuple listing input clock names.
66-
Required elements: "t0_clk"
67+
Required elements: "t0_clk", "slow_clk"
6768
Optional elements: "t1_clk", "t2_clk"
6869
- clocks: phandles to input clocks.
6970

@@ -91,12 +92,14 @@ RSTC Reset Controller required properties:
9192
- compatible: Should be "atmel,<chip>-rstc".
9293
<chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
9394
- reg: Should contain registers location and length
95+
- clocks: phandle to input clock.
9496

9597
Example:
9698

9799
rstc@fffffd00 {
98100
compatible = "atmel,at91sam9260-rstc";
99101
reg = <0xfffffd00 0x10>;
102+
clocks = <&clk32k>;
100103
};
101104

102105
RAMC SDRAM/DDR Controller required properties:
@@ -119,6 +122,7 @@ required properties:
119122
- compatible: Should be "atmel,<chip>-shdwc".
120123
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
121124
- reg: Should contain registers location and length
125+
- clocks: phandle to input clock.
122126

123127
optional properties:
124128
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
@@ -137,9 +141,10 @@ optional at91sam9x5 properties:
137141

138142
Example:
139143

140-
rstc@fffffd00 {
141-
compatible = "atmel,at91sam9260-rstc";
142-
reg = <0xfffffd00 0x10>;
144+
shdwc@fffffd10 {
145+
compatible = "atmel,at91sam9260-shdwc";
146+
reg = <0xfffffd10 0x10>;
147+
clocks = <&clk32k>;
143148
};
144149

145150
Special Function Registers (SFR)

‎Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
Raspberry Pi VideoCore firmware driver
2+
3+
Required properties:
4+
5+
- compatible: Should be "raspberrypi,bcm2835-firmware"
6+
- mboxes: Phandle to the firmware device's Mailbox.
7+
(See: ../mailbox/mailbox.txt for more information)
8+
9+
Example:
10+
11+
firmware {
12+
compatible = "raspberrypi,bcm2835-firmware";
13+
mboxes = <&mailbox>;
14+
};

‎Documentation/devicetree/bindings/arm/marvell,kirkwood.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,8 @@ And in addition, the compatible shall be extended with the specific
2020
board. Currently known boards are:
2121

2222
"buffalo,lschlv2"
23+
"buffalo,lswvl"
24+
"buffalo,lswxl"
2325
"buffalo,lsxhl"
2426
"buffalo,lsxl"
2527
"dlink,dns-320"

‎Documentation/devicetree/bindings/arm/mediatek.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property:
55
Required root node property:
66

77
compatible: Must contain one of
8+
"mediatek,mt6580"
89
"mediatek,mt6589"
910
"mediatek,mt6592"
1011
"mediatek,mt8127"
@@ -14,6 +15,9 @@ compatible: Must contain one of
1415

1516
Supported boards:
1617

18+
- Evaluation board for MT6580:
19+
Required root node properties:
20+
- compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
1721
- bq Aquaris5 smart phone:
1822
Required root node properties:
1923
- compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";

‎Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ Required properties:
1111
"mediatek,mt6592-sysirq"
1212
"mediatek,mt6589-sysirq"
1313
"mediatek,mt6582-sysirq"
14+
"mediatek,mt6580-sysirq"
1415
"mediatek,mt6577-sysirq"
1516
- interrupt-controller : Identifies the node as an interrupt controller
1617
- #interrupt-cells : Use the same format as specified by GIC in

‎Documentation/devicetree/bindings/arm/omap/omap.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,9 @@ Boards:
135135
- AM335X OrionLXm : Substation Automation Platform
136136
compatible = "novatech,am335x-lxm", "ti,am33xx"
137137

138+
- AM335X phyBOARD-WEGA: Single Board Computer dev kit
139+
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
140+
138141
- OMAP5 EVM : Evaluation Module
139142
compatible = "ti,omap5-evm", "ti,omap5"
140143

‎Documentation/devicetree/bindings/arm/rockchip.txt

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,3 +26,38 @@ Rockchip platforms device tree bindings
2626
- ChipSPARK PopMetal-RK3288 board:
2727
Required root node properties:
2828
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
29+
30+
- Netxeon R89 board:
31+
Required root node properties:
32+
- compatible = "netxeon,r89", "rockchip,rk3288";
33+
34+
- Google Jerry (Hisense Chromebook C11 and more):
35+
Required root node properties:
36+
- compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
37+
"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
38+
"google,veyron-jerry-rev3", "google,veyron-jerry",
39+
"google,veyron", "rockchip,rk3288";
40+
41+
- Google Minnie (Asus Chromebook Flip C100P):
42+
Required root node properties:
43+
- compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
44+
"google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
45+
"google,veyron-minnie-rev0", "google,veyron-minnie",
46+
"google,veyron", "rockchip,rk3288";
47+
48+
- Google Pinky (dev-board):
49+
Required root node properties:
50+
- compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
51+
"google,veyron", "rockchip,rk3288";
52+
53+
- Google Speedy (Asus C201 Chromebook):
54+
Required root node properties:
55+
- compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
56+
"google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
57+
"google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
58+
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
59+
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
60+
61+
- Rockchip R88 board:
62+
Required root node properties:
63+
- compatible = "rockchip,r88", "rockchip,rk3368";

‎Documentation/devicetree/bindings/clock/imx6ul-clock.txt

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
* Clock bindings for Freescale i.MX6 UltraLite
2+
3+
Required properties:
4+
- compatible: Should be "fsl,imx6ul-ccm"
5+
- reg: Address and length of the register set
6+
- #clock-cells: Should be <1>
7+
- clocks: list of clock specifiers, must contain an entry for each required
8+
entry in clock-names
9+
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
10+
11+
The clock consumer should specify the desired clock by having the clock
12+
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h
13+
for the full list of i.MX6 UltraLite clock IDs.

‎Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ Required properties:
2121
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
2222
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
2323
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
24-
"st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
25-
"st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
24+
"sst,plls-c32-cx_0", "st,clkgen-plls-c32"
25+
"sst,plls-c32-cx_1", "st,clkgen-plls-c32"
2626

2727
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
2828
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"

‎Documentation/devicetree/bindings/memory-controllers/synopsys.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,9 @@
11
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
22

3+
This controller has an optional ECC support in half-bus width (16-bit)
4+
configuration. The ECC controller corrects one bit error and detects
5+
two bit errors.
6+
37
Required properties:
48
- compatible: Should be 'xlnx,zynq-ddrc-a05'
59
- reg: Base address and size of the controllers memory area

‎Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
* Freescale i.MX6 UltraLite IOMUX Controller
2+
3+
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4+
and usage.
5+
6+
Required properties:
7+
- compatible: "fsl,imx6ul-iomuxc"
8+
- fsl,pins: each entry consists of 6 integers and represents the mux and config
9+
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
10+
input_val> are specified using a PIN_FUNC_ID macro, which can be found in
11+
imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
12+
the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
13+
Reference Manual for detailed CONFIG settings.
14+
15+
CONFIG bits definition:
16+
PAD_CTL_HYS (1 << 16)
17+
PAD_CTL_PUS_100K_DOWN (0 << 14)
18+
PAD_CTL_PUS_47K_UP (1 << 14)
19+
PAD_CTL_PUS_100K_UP (2 << 14)
20+
PAD_CTL_PUS_22K_UP (3 << 14)
21+
PAD_CTL_PUE (1 << 13)
22+
PAD_CTL_PKE (1 << 12)
23+
PAD_CTL_ODE (1 << 11)
24+
PAD_CTL_SPEED_LOW (0 << 6)
25+
PAD_CTL_SPEED_MED (1 << 6)
26+
PAD_CTL_SPEED_HIGH (3 << 6)
27+
PAD_CTL_DSE_DISABLE (0 << 3)
28+
PAD_CTL_DSE_260ohm (1 << 3)
29+
PAD_CTL_DSE_130ohm (2 << 3)
30+
PAD_CTL_DSE_87ohm (3 << 3)
31+
PAD_CTL_DSE_65ohm (4 << 3)
32+
PAD_CTL_DSE_52ohm (5 << 3)
33+
PAD_CTL_DSE_43ohm (6 << 3)
34+
PAD_CTL_DSE_37ohm (7 << 3)
35+
PAD_CTL_SRE_FAST (1 << 0)
36+
PAD_CTL_SRE_SLOW (0 << 0)

‎Documentation/devicetree/bindings/reset/socfpga-reset.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,13 @@ Altera SOCFPGA Reset Manager
33
Required properties:
44
- compatible : "altr,rst-mgr"
55
- reg : Should contain 1 register ranges(address and length)
6+
- altr,modrst-offset : Should contain the offset of the first modrst register.
67
- #reset-cells: 1
78

89
Example:
910
rstmgr@ffd05000 {
1011
#reset-cells = <1>;
1112
compatible = "altr,rst-mgr";
1213
reg = <0xffd05000 0x1000>;
14+
altr,modrst-offset = <0x10>;
1315
};

‎Documentation/devicetree/bindings/rtc/atmel,at91rm9200-rtc.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,13 @@ Required properties:
55
- reg: physical base address of the controller and length of memory mapped
66
region.
77
- interrupts: rtc alarm/event interrupt
8+
- clocks: phandle to input clock.
89

910
Example:
1011

1112
rtc@fffffe00 {
1213
compatible = "atmel,at91rm9200-rtc";
1314
reg = <0xfffffe00 0x100>;
1415
interrupts = <1 4 7>;
16+
clocks = <&clk32k>;
1517
};

‎Documentation/devicetree/bindings/rtc/rtc-omap.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ Required properties:
88
Wakeup generation for event Alarm. It can also be
99
used to control an external PMIC via the
1010
pmic_power_en pin.
11+
- "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
1112
- reg: Address range of rtc register set
1213
- interrupts: rtc timer, alarm interrupts in order
1314
- interrupt-parent: phandle for the interrupt controller

‎Documentation/devicetree/bindings/serial/mtk-uart.txt

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,9 @@ Required properties:
77
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
88
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
99
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
10+
* "mediatek,mt6580-uart" for MT6580 compatible UARTS
1011
* "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
11-
MT6577)
12+
MT6580, MT6577)
1213

1314
- reg: The base address of the UART register bank.
1415

‎Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,11 @@ Mediatek MT6577, MT6572 and MT6589 Timers
22
---------------------------------------
33

44
Required properties:
5-
- compatible: Should be "mediatek,mt6577-timer"
5+
- compatible should contain:
6+
* "mediatek,mt6589-timer" for MT6589 compatible timers
7+
* "mediatek,mt6580-timer" for MT6580 compatible timers
8+
* "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580,
9+
MT6577)
610
- reg: Should contain location and length for timers register.
711
- clocks: Clocks driving the timer hardware. This list should include two
812
clocks. The order is system clock and as second clock the RTC clock.

‎Documentation/devicetree/bindings/vendor-prefixes.txt

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,7 @@ chipone ChipOne
4646
chipspark ChipSPARK
4747
chrp Common Hardware Reference Platform
4848
chunghwa Chunghwa Picture Tubes Ltd.
49+
ciaa Computadora Industrial Abierta Argentina
4950
cirrus Cirrus Logic, Inc.
5051
cloudengines Cloud Engines, Inc.
5152
cnm Chips&Media, Inc.
@@ -135,6 +136,7 @@ mitsubishi Mitsubishi Electric Corporation
135136
mosaixtech Mosaix Technologies, Inc.
136137
moxa Moxa
137138
mpl MPL AG
139+
msi Micro-Star International Co. Ltd.
138140
mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
139141
mundoreader Mundo Reader S.L.
140142
murata Murata Manufacturing Co., Ltd.
@@ -143,6 +145,7 @@ national National Semiconductor
143145
neonode Neonode Inc.
144146
netgear NETGEAR
145147
netlogic Broadcom Corporation (formerly NetLogic Microsystems)
148+
netxeon Shenzhen Netxeon Technology CO., LTD
146149
newhaven Newhaven Display International
147150
nintendo Nintendo
148151
nokia Nokia

‎Documentation/devicetree/bindings/watchdog/atmel-wdt.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ Required properties:
66
- compatible: must be "atmel,at91sam9260-wdt".
77
- reg: physical base address of the controller and length of memory mapped
88
region.
9+
- clocks: phandle to input clock.
910

1011
Optional properties:
1112
- timeout-sec: contains the watchdog timeout in seconds.
@@ -39,6 +40,7 @@ Example:
3940
compatible = "atmel,at91sam9260-wdt";
4041
reg = <0xfffffd40 0x10>;
4142
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
43+
clocks = <&clk32k>;
4244
timeout-sec = <15>;
4345
atmel,watchdog-type = "hardware";
4446
atmel,reset-type = "all";

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