@@ -1668,6 +1668,18 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
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if (rc )
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return rc ;
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+ if (IS_PF (cdev ) && test_bit (QED_MF_8021AD_TAGGING ,
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+ & cdev -> mf_bits )) {
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+ STORE_RT_REG (p_hwfn , PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET ,
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+ ETH_P_8021AD );
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+ STORE_RT_REG (p_hwfn , NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET ,
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+ ETH_P_8021AD );
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+ STORE_RT_REG (p_hwfn , PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET ,
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+ ETH_P_8021AD );
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+ STORE_RT_REG (p_hwfn , DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET ,
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+ ETH_P_8021AD );
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+ }
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+
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qed_fill_load_req_params (& load_req_params ,
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p_params -> p_drv_load_params );
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rc = qed_mcp_load_req (p_hwfn , p_hwfn -> p_main_ptt ,
@@ -2630,39 +2642,51 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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link -> pause .autoneg ,
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p_caps -> default_eee , p_caps -> eee_lpi_timer );
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- /* Read Multi-function information from shmem */
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- addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
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- offsetof(struct nvm_cfg1 , glob ) +
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- offsetof(struct nvm_cfg1_glob , generic_cont0 );
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+ if (IS_LEAD_HWFN (p_hwfn )) {
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+ struct qed_dev * cdev = p_hwfn -> cdev ;
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- generic_cont0 = qed_rd (p_hwfn , p_ptt , addr );
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+ /* Read Multi-function information from shmem */
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+ addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
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+ offsetof(struct nvm_cfg1 , glob ) +
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+ offsetof(struct nvm_cfg1_glob , generic_cont0 );
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- mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK ) >>
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- NVM_CFG1_GLOB_MF_MODE_OFFSET ;
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+ generic_cont0 = qed_rd (p_hwfn , p_ptt , addr );
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- switch (mf_mode ) {
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- case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED :
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- p_hwfn -> cdev -> mf_bits = BIT (QED_MF_OVLAN_CLSS );
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- break ;
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- case NVM_CFG1_GLOB_MF_MODE_NPAR1_0 :
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- p_hwfn -> cdev -> mf_bits = BIT (QED_MF_LLH_MAC_CLSS ) |
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+ mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK ) >>
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+ NVM_CFG1_GLOB_MF_MODE_OFFSET ;
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+
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+ switch (mf_mode ) {
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+ case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED :
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+ cdev -> mf_bits = BIT (QED_MF_OVLAN_CLSS );
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+ break ;
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+ case NVM_CFG1_GLOB_MF_MODE_BD :
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+ cdev -> mf_bits = BIT (QED_MF_OVLAN_CLSS ) |
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+ BIT (QED_MF_LLH_PROTO_CLSS ) |
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+ BIT (QED_MF_8021AD_TAGGING );
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+ break ;
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+ case NVM_CFG1_GLOB_MF_MODE_NPAR1_0 :
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+ cdev -> mf_bits = BIT (QED_MF_LLH_MAC_CLSS ) |
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BIT (QED_MF_LLH_PROTO_CLSS ) |
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BIT (QED_MF_LL2_NON_UNICAST ) |
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BIT (QED_MF_INTER_PF_SWITCH );
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- break ;
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- case NVM_CFG1_GLOB_MF_MODE_DEFAULT :
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- p_hwfn -> cdev -> mf_bits = BIT (QED_MF_LLH_MAC_CLSS ) |
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+ break ;
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+ case NVM_CFG1_GLOB_MF_MODE_DEFAULT :
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+ cdev -> mf_bits = BIT (QED_MF_LLH_MAC_CLSS ) |
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BIT (QED_MF_LLH_PROTO_CLSS ) |
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BIT (QED_MF_LL2_NON_UNICAST );
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- if (QED_IS_BB (p_hwfn -> cdev ))
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- p_hwfn -> cdev -> mf_bits |= BIT (QED_MF_NEED_DEF_PF );
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- break ;
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+ if (QED_IS_BB (p_hwfn -> cdev ))
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+ cdev -> mf_bits |= BIT (QED_MF_NEED_DEF_PF );
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+ break ;
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+ }
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+
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+ DP_INFO (p_hwfn , "Multi function mode is 0x%lx\n" ,
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+ cdev -> mf_bits );
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}
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DP_INFO (p_hwfn , "Multi function mode is 0x%lx\n" ,
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p_hwfn -> cdev -> mf_bits );
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- /* Read Multi-function information from shmem */
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+ /* Read device capabilities information from shmem */
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addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
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offsetof(struct nvm_cfg1 , glob ) +
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offsetof(struct nvm_cfg1_glob , device_capabilities );
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