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davidhildenbrandakpm00
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microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE
Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit from the type. Generic MM currently only uses 5 bits for the type (MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused. The shift by 2 when converting between PTE and arch-specific swap entry makes the swap PTE layout a little bit harder to decipher. While at it, drop the comment from paulus---copy-and-paste leftover from powerpc where we actually have _PAGE_HASHPTE---and mask the type in __swp_entry_to_pte() as well. Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: David Hildenbrand <[email protected]> Cc: Michal Simek <[email protected]> Signed-off-by: Andrew Morton <[email protected]>
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arch/m68k/include/asm/mcf_pgtable.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -46,8 +46,8 @@
4646
#define _CACHEMASK040 (~0x060)
4747
#define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */
4848

49-
/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
50-
#define _PAGE_SWP_EXCLUSIVE 0x080
49+
/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
50+
#define _PAGE_SWP_EXCLUSIVE CF_PAGE_NOCACHE
5151

5252
/*
5353
* Externally used page protection values.

arch/microblaze/include/asm/pgtable.h

Lines changed: 35 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address);
131131
* of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
132132
* miss handler. Bit 27 is PAGE_USER, thus selecting the correct
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* zone.
134-
* - PRESENT *must* be in the bottom two bits because swap cache
135-
* entries use the top 30 bits. Because 4xx doesn't support SMP
136-
* anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30
137-
* is cleared in the TLB miss handler before the TLB entry is loaded.
134+
* - PRESENT *must* be in the bottom two bits because swap PTEs use the top
135+
* 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we
136+
* borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler
137+
* before the TLB entry is loaded.
138138
* - All other bits of the PTE are loaded into TLBLO without
139139
* * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
140140
* software PTE bits. We actually use bits 21, 24, 25, and
@@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address);
155155
#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
156156
#define _PMD_PRESENT PAGE_MASK
157157

158+
/* We borrow bit 24 to store the exclusive marker in swap PTEs. */
159+
#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
160+
158161
/*
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* Some bits are unused...
160163
*/
@@ -393,18 +396,40 @@ static inline unsigned long pmd_page_vaddr(pmd_t pmd)
393396
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
394397

395398
/*
396-
* Encode and decode a swap entry.
397-
* Note that the bits we use in a PTE for representing a swap entry
398-
* must not include the _PAGE_PRESENT bit, or the _PAGE_HASHPTE bit
399-
* (if used). -- paulus
399+
* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
400+
* are !pte_none() && !pte_present().
401+
*
402+
* 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
403+
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
404+
* <------------------ offset -------------------> E < type -> 0 0
405+
*
406+
* E is the exclusive marker that is not stored in swap entries.
400407
*/
401-
#define __swp_type(entry) ((entry).val & 0x3f)
408+
#define __swp_type(entry) ((entry).val & 0x1f)
402409
#define __swp_offset(entry) ((entry).val >> 6)
403410
#define __swp_entry(type, offset) \
404-
((swp_entry_t) { (type) | ((offset) << 6) })
411+
((swp_entry_t) { ((type) & 0x1f) | ((offset) << 6) })
405412
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
406413
#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
407414

415+
#define __HAVE_ARCH_PTE_SWP_EXCLUSIVE
416+
static inline int pte_swp_exclusive(pte_t pte)
417+
{
418+
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
419+
}
420+
421+
static inline pte_t pte_swp_mkexclusive(pte_t pte)
422+
{
423+
pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
424+
return pte;
425+
}
426+
427+
static inline pte_t pte_swp_clear_exclusive(pte_t pte)
428+
{
429+
pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
430+
return pte;
431+
}
432+
408433
extern unsigned long iopa(unsigned long addr);
409434

410435
/* Values for nocacheflag and cmode */

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