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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd: "This is the first batch of clk driver fixes for this release. We have a handful of fixes for the uniphier clk driver that was introduced recently, as well as Kconfig option hiding, module autoloading markings, and a few fixes for clk_hw based registration patches that went in this merge window" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: at91: Fix a return value in case of error clk: uniphier: rename MIO clock to SD clock for Pro5, PXs2, LD20 SoCs clk: uniphier: fix memory overrun bug clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init clk: mvebu: armada-37xx-periph: Fix the clock gate flag clk: bcm2835: Clamp the PLL's requested rate to the hardware limits. clk: max77686: fix number of clocks setup for clk_hw based registration clk: mvebu: armada-37xx-periph: Fix the clock provider registration clk: core: add __init decoration for CLK_OF_DECLARE_DRIVER function clk: mediatek: Add hardware dependency clk: samsung: clk-exynos-audss: Fix module autoload clk: uniphier: fix type of variable passed to regmap_read() clk: uniphier: add system clock support for sLD3 SoC
2 parents 1ce5bdb + 91bbc17 commit b5cd891

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13 files changed

+41
-35
lines changed

13 files changed

+41
-35
lines changed

‎Documentation/devicetree/bindings/clock/uniphier-clock.txt

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ Example:
2424
reg = <0x61840000 0x4000>;
2525

2626
clock {
27-
compatible = "socionext,uniphier-ld20-clock";
27+
compatible = "socionext,uniphier-ld11-clock";
2828
#clock-cells = <1>;
2929
};
3030

@@ -43,19 +43,19 @@ Provided clocks:
4343
21: USB3 ch1 PHY1
4444

4545

46-
Media I/O (MIO) clock
47-
---------------------
46+
Media I/O (MIO) clock, SD clock
47+
-------------------------------
4848

4949
Required properties:
5050
- compatible: should be one of the following:
5151
"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
5252
"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
5353
"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
5454
"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
55-
"socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
56-
"socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
55+
"socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
56+
"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
5757
"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
58-
"socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
58+
"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
5959
- #clock-cells: should be 1.
6060

6161
Example:
@@ -66,7 +66,7 @@ Example:
6666
reg = <0x59810000 0x800>;
6767

6868
clock {
69-
compatible = "socionext,uniphier-ld20-mio-clock";
69+
compatible = "socionext,uniphier-ld11-mio-clock";
7070
#clock-cells = <1>;
7171
};
7272

@@ -112,7 +112,7 @@ Example:
112112
reg = <0x59820000 0x200>;
113113

114114
clock {
115-
compatible = "socionext,uniphier-ld20-peri-clock";
115+
compatible = "socionext,uniphier-ld11-peri-clock";
116116
#clock-cells = <1>;
117117
};
118118

‎drivers/clk/at91/clk-programmable.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -203,7 +203,7 @@ at91_clk_register_programmable(struct regmap *regmap,
203203
ret = clk_hw_register(NULL, &prog->hw);
204204
if (ret) {
205205
kfree(prog);
206-
hw = &prog->hw;
206+
hw = ERR_PTR(ret);
207207
}
208208

209209
return hw;

‎drivers/clk/bcm/clk-bcm2835.c

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -502,8 +502,12 @@ static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
502502
static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
503503
unsigned long *parent_rate)
504504
{
505+
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
506+
const struct bcm2835_pll_data *data = pll->data;
505507
u32 ndiv, fdiv;
506508

509+
rate = clamp(rate, data->min_rate, data->max_rate);
510+
507511
bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
508512

509513
return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
@@ -608,13 +612,6 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw,
608612
u32 ana[4];
609613
int i;
610614

611-
if (rate < data->min_rate || rate > data->max_rate) {
612-
dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n",
613-
clk_hw_get_name(hw), rate,
614-
data->min_rate, data->max_rate);
615-
return -EINVAL;
616-
}
617-
618615
if (rate > data->max_fb_rate) {
619616
use_fb_prediv = true;
620617
rate /= 2;

‎drivers/clk/clk-max77686.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,7 @@ static int max77686_clk_probe(struct platform_device *pdev)
216216
return -EINVAL;
217217
}
218218

219+
drv_data->num_clks = num_clks;
219220
drv_data->max_clk_data = devm_kcalloc(dev, num_clks,
220221
sizeof(*drv_data->max_clk_data),
221222
GFP_KERNEL);

‎drivers/clk/hisilicon/clk-hi6220.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@ static void __init hi6220_clk_sys_init(struct device_node *np)
195195
hi6220_clk_register_divider(hi6220_div_clks_sys,
196196
ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
197197
}
198-
CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
198+
CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
199199

200200

201201
/* clocks in media controller */
@@ -252,7 +252,7 @@ static void __init hi6220_clk_media_init(struct device_node *np)
252252
hi6220_clk_register_divider(hi6220_div_clks_media,
253253
ARRAY_SIZE(hi6220_div_clks_media), clk_data);
254254
}
255-
CLK_OF_DECLARE(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
255+
CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
256256

257257

258258
/* clocks in pmctrl */

‎drivers/clk/mediatek/Kconfig

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,15 @@ config COMMON_CLK_MEDIATEK
88

99
config COMMON_CLK_MT8135
1010
bool "Clock driver for Mediatek MT8135"
11+
depends on ARCH_MEDIATEK || COMPILE_TEST
1112
select COMMON_CLK_MEDIATEK
1213
default ARCH_MEDIATEK
1314
---help---
1415
This driver supports Mediatek MT8135 clocks.
1516

1617
config COMMON_CLK_MT8173
1718
bool "Clock driver for Mediatek MT8173"
19+
depends on ARCH_MEDIATEK || COMPILE_TEST
1820
select COMMON_CLK_MEDIATEK
1921
default ARCH_MEDIATEK
2022
---help---

‎drivers/clk/mvebu/armada-37xx-periph.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -305,7 +305,7 @@ static const struct of_device_id armada_3700_periph_clock_of_match[] = {
305305
};
306306
static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
307307
void __iomem *reg, spinlock_t *lock,
308-
struct device *dev, struct clk_hw *hw)
308+
struct device *dev, struct clk_hw **hw)
309309
{
310310
const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
311311
*rate_ops = NULL;
@@ -329,6 +329,7 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
329329
gate->lock = lock;
330330
gate_ops = gate_hw->init->ops;
331331
gate->reg = reg + (u64)gate->reg;
332+
gate->flags = CLK_GATE_SET_TO_DISABLE;
332333
}
333334

334335
if (data->rate_hw) {
@@ -353,13 +354,13 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
353354
}
354355
}
355356

356-
hw = clk_hw_register_composite(dev, data->name, data->parent_names,
357+
*hw = clk_hw_register_composite(dev, data->name, data->parent_names,
357358
data->num_parents, mux_hw,
358359
mux_ops, rate_hw, rate_ops,
359360
gate_hw, gate_ops, CLK_IGNORE_UNUSED);
360361

361-
if (IS_ERR(hw))
362-
return PTR_ERR(hw);
362+
if (IS_ERR(*hw))
363+
return PTR_ERR(*hw);
363364

364365
return 0;
365366
}
@@ -400,7 +401,7 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
400401
spin_lock_init(&driver_data->lock);
401402

402403
for (i = 0; i < num_periph; i++) {
403-
struct clk_hw *hw = driver_data->hw_data->hws[i];
404+
struct clk_hw **hw = &driver_data->hw_data->hws[i];
404405

405406
if (armada_3700_add_composite_clk(&data[i], reg,
406407
&driver_data->lock, dev, hw))

‎drivers/clk/samsung/clk-exynos-audss.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,7 @@ static const struct of_device_id exynos_audss_clk_of_match[] = {
106106
},
107107
{ },
108108
};
109+
MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
109110

110111
static void exynos_audss_clk_teardown(void)
111112
{

‎drivers/clk/uniphier/clk-uniphier-core.c

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ static int uniphier_clk_probe(struct platform_device *pdev)
7979
hw_data->num = clk_num;
8080

8181
/* avoid returning NULL for unused idx */
82-
for (; clk_num >= 0; clk_num--)
82+
while (--clk_num >= 0)
8383
hw_data->hws[clk_num] = ERR_PTR(-EINVAL);
8484

8585
for (p = data; p->name; p++) {
@@ -110,6 +110,10 @@ static int uniphier_clk_remove(struct platform_device *pdev)
110110

111111
static const struct of_device_id uniphier_clk_match[] = {
112112
/* System clock */
113+
{
114+
.compatible = "socionext,uniphier-sld3-clock",
115+
.data = uniphier_sld3_sys_clk_data,
116+
},
113117
{
114118
.compatible = "socionext,uniphier-ld4-clock",
115119
.data = uniphier_ld4_sys_clk_data,
@@ -138,7 +142,7 @@ static const struct of_device_id uniphier_clk_match[] = {
138142
.compatible = "socionext,uniphier-ld20-clock",
139143
.data = uniphier_ld20_sys_clk_data,
140144
},
141-
/* Media I/O clock */
145+
/* Media I/O clock, SD clock */
142146
{
143147
.compatible = "socionext,uniphier-sld3-mio-clock",
144148
.data = uniphier_sld3_mio_clk_data,
@@ -156,20 +160,20 @@ static const struct of_device_id uniphier_clk_match[] = {
156160
.data = uniphier_sld3_mio_clk_data,
157161
},
158162
{
159-
.compatible = "socionext,uniphier-pro5-mio-clock",
160-
.data = uniphier_pro5_mio_clk_data,
163+
.compatible = "socionext,uniphier-pro5-sd-clock",
164+
.data = uniphier_pro5_sd_clk_data,
161165
},
162166
{
163-
.compatible = "socionext,uniphier-pxs2-mio-clock",
164-
.data = uniphier_pro5_mio_clk_data,
167+
.compatible = "socionext,uniphier-pxs2-sd-clock",
168+
.data = uniphier_pro5_sd_clk_data,
165169
},
166170
{
167171
.compatible = "socionext,uniphier-ld11-mio-clock",
168172
.data = uniphier_sld3_mio_clk_data,
169173
},
170174
{
171-
.compatible = "socionext,uniphier-ld20-mio-clock",
172-
.data = uniphier_pro5_mio_clk_data,
175+
.compatible = "socionext,uniphier-ld20-sd-clock",
176+
.data = uniphier_pro5_sd_clk_data,
173177
},
174178
/* Peripheral clock */
175179
{

‎drivers/clk/uniphier/clk-uniphier-mio.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
9393
{ /* sentinel */ }
9494
};
9595

96-
const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {
96+
const struct uniphier_clk_data uniphier_pro5_sd_clk_data[] = {
9797
UNIPHIER_MIO_CLK_SD_FIXED,
9898
UNIPHIER_MIO_CLK_SD(0, 0),
9999
UNIPHIER_MIO_CLK_SD(1, 1),

‎drivers/clk/uniphier/clk-uniphier-mux.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
4242
struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
4343
int num_parents = clk_hw_get_num_parents(hw);
4444
int ret;
45-
u32 val;
45+
unsigned int val;
4646
u8 i;
4747

4848
ret = regmap_read(mux->regmap, mux->reg, &val);

‎drivers/clk/uniphier/clk-uniphier.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
115115
extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
116116
extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
117117
extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
118-
extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];
118+
extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
119119
extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
120120
extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
121121

‎include/linux/clk-provider.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -785,7 +785,7 @@ extern struct of_device_id __clk_of_table;
785785
* routines, one at of_clk_init(), and one at platform device probe
786786
*/
787787
#define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
788-
static void name##_of_clk_init_driver(struct device_node *np) \
788+
static void __init name##_of_clk_init_driver(struct device_node *np) \
789789
{ \
790790
of_node_clear_flag(np, OF_POPULATED); \
791791
fn(np); \

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