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Andi KleenH. Peter Anvin
authored andcommitted
x86, mce: factor out duplicated struct mce setup into one function
Impact: cleanup This merely factors out duplicated code to set up the initial struct mce state into a single function. Signed-off-by: Andi Kleen <[email protected]> Signed-off-by: H. Peter Anvin <[email protected]>
1 parent 0d7482e commit b5f2fa4

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4 files changed

+18
-14
lines changed

4 files changed

+18
-14
lines changed

arch/x86/include/asm/mce.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,6 +90,7 @@ extern int mce_disabled;
9090

9191
#include <asm/atomic.h>
9292

93+
void mce_setup(struct mce *m);
9394
void mce_log(struct mce *m);
9495
DECLARE_PER_CPU(struct sys_device, device_mce);
9596
extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
@@ -106,7 +107,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c);
106107
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
107108
#endif
108109

109-
void mce_log_therm_throt_event(unsigned int cpu, __u64 status);
110+
void mce_log_therm_throt_event(__u64 status);
110111

111112
extern atomic_t mce_entry;
112113

arch/x86/kernel/cpu/mcheck/mce_64.c

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,14 @@ static char *trigger_argv[2] = { trigger, NULL };
6565

6666
static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
6767

68+
/* Do initial initialization of a struct mce */
69+
void mce_setup(struct mce *m)
70+
{
71+
memset(m, 0, sizeof(struct mce));
72+
m->cpu = smp_processor_id();
73+
rdtscll(m->tsc);
74+
}
75+
6876
/*
6977
* Lockless MCE logging infrastructure.
7078
* This avoids deadlocks on printk locks without having to break locks. Also
@@ -208,8 +216,8 @@ void do_machine_check(struct pt_regs * regs, long error_code)
208216
|| !banks)
209217
goto out2;
210218

211-
memset(&m, 0, sizeof(struct mce));
212-
m.cpu = smp_processor_id();
219+
mce_setup(&m);
220+
213221
rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
214222
/* if the restart IP is not valid, we're done for */
215223
if (!(m.mcgstatus & MCG_STATUS_RIPV))
@@ -225,7 +233,6 @@ void do_machine_check(struct pt_regs * regs, long error_code)
225233
m.misc = 0;
226234
m.addr = 0;
227235
m.bank = i;
228-
m.tsc = 0;
229236

230237
rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status);
231238
if ((m.status & MCI_STATUS_VAL) == 0)
@@ -252,8 +259,8 @@ void do_machine_check(struct pt_regs * regs, long error_code)
252259
rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr);
253260

254261
mce_get_rip(&m, regs);
255-
if (error_code >= 0)
256-
rdtscll(m.tsc);
262+
if (error_code < 0)
263+
m.tsc = 0;
257264
if (error_code != -2)
258265
mce_log(&m);
259266

@@ -341,15 +348,13 @@ void do_machine_check(struct pt_regs * regs, long error_code)
341348
* and historically has been the register value of the
342349
* MSR_IA32_THERMAL_STATUS (Intel) msr.
343350
*/
344-
void mce_log_therm_throt_event(unsigned int cpu, __u64 status)
351+
void mce_log_therm_throt_event(__u64 status)
345352
{
346353
struct mce m;
347354

348-
memset(&m, 0, sizeof(m));
349-
m.cpu = cpu;
355+
mce_setup(&m);
350356
m.bank = MCE_THERMAL_BANK;
351357
m.status = status;
352-
rdtscll(m.tsc);
353358
mce_log(&m);
354359
}
355360
#endif /* CONFIG_X86_MCE_INTEL */

arch/x86/kernel/cpu/mcheck/mce_amd_64.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -197,9 +197,7 @@ asmlinkage void mce_threshold_interrupt(void)
197197
exit_idle();
198198
irq_enter();
199199

200-
memset(&m, 0, sizeof(m));
201-
rdtscll(m.tsc);
202-
m.cpu = smp_processor_id();
200+
mce_setup(&m);
203201

204202
/* assume first bank caused it */
205203
for (bank = 0; bank < NR_BANKS; ++bank) {

arch/x86/kernel/cpu/mcheck/mce_intel_64.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ asmlinkage void smp_thermal_interrupt(void)
2424

2525
rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
2626
if (therm_throt_process(msr_val & 1))
27-
mce_log_therm_throt_event(smp_processor_id(), msr_val);
27+
mce_log_therm_throt_event(msr_val);
2828

2929
inc_irq_stat(irq_thermal_count);
3030
irq_exit();

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