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24 | 24 | #include <linux/acpi_iort.h>
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25 | 25 | #include <linux/bitfield.h>
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26 | 26 | #include <linux/bitops.h>
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| 27 | +#include <linux/crash_dump.h> |
27 | 28 | #include <linux/delay.h>
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28 | 29 | #include <linux/dma-iommu.h>
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29 | 30 | #include <linux/err.h>
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@@ -2212,8 +2213,12 @@ static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr)
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2212 | 2213 | reg &= ~clr;
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2213 | 2214 | reg |= set;
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2214 | 2215 | writel_relaxed(reg | GBPA_UPDATE, gbpa);
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2215 |
| - return readl_relaxed_poll_timeout(gbpa, reg, !(reg & GBPA_UPDATE), |
2216 |
| - 1, ARM_SMMU_POLL_TIMEOUT_US); |
| 2216 | + ret = readl_relaxed_poll_timeout(gbpa, reg, !(reg & GBPA_UPDATE), |
| 2217 | + 1, ARM_SMMU_POLL_TIMEOUT_US); |
| 2218 | + |
| 2219 | + if (ret) |
| 2220 | + dev_err(smmu->dev, "GBPA not responding to update\n"); |
| 2221 | + return ret; |
2217 | 2222 | }
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2218 | 2223 |
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2219 | 2224 | static void arm_smmu_free_msis(void *data)
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@@ -2393,8 +2398,15 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
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2393 | 2398 |
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2394 | 2399 | /* Clear CR0 and sync (disables SMMU and queue processing) */
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2395 | 2400 | reg = readl_relaxed(smmu->base + ARM_SMMU_CR0);
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2396 |
| - if (reg & CR0_SMMUEN) |
| 2401 | + if (reg & CR0_SMMUEN) { |
| 2402 | + if (is_kdump_kernel()) { |
| 2403 | + arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); |
| 2404 | + arm_smmu_device_disable(smmu); |
| 2405 | + return -EBUSY; |
| 2406 | + } |
| 2407 | + |
2397 | 2408 | dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n");
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| 2409 | + } |
2398 | 2410 |
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2399 | 2411 | ret = arm_smmu_device_disable(smmu);
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2400 | 2412 | if (ret)
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@@ -2492,10 +2504,8 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass)
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2492 | 2504 | enables |= CR0_SMMUEN;
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2493 | 2505 | } else {
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2494 | 2506 | ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT);
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2495 |
| - if (ret) { |
2496 |
| - dev_err(smmu->dev, "GBPA not responding to update\n"); |
| 2507 | + if (ret) |
2497 | 2508 | return ret;
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2498 |
| - } |
2499 | 2509 | }
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2500 | 2510 | ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0,
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2501 | 2511 | ARM_SMMU_CR0ACK);
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