@@ -346,7 +346,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
346
346
MLX4_GET (field , outbox , QUERY_DEV_CAP_VL_PORT_OFFSET );
347
347
dev_cap -> max_vl [i ] = field >> 4 ;
348
348
MLX4_GET (field , outbox , QUERY_DEV_CAP_MTU_WIDTH_OFFSET );
349
- dev_cap -> max_mtu [i ] = field >> 4 ;
349
+ dev_cap -> ib_mtu [i ] = field >> 4 ;
350
350
dev_cap -> max_port_width [i ] = field & 0xf ;
351
351
MLX4_GET (field , outbox , QUERY_DEV_CAP_MAX_GID_OFFSET );
352
352
dev_cap -> max_gids [i ] = 1 << (field & 0xf );
@@ -355,8 +355,10 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
355
355
}
356
356
} else {
357
357
#define QUERY_PORT_MTU_OFFSET 0x01
358
+ #define QUERY_PORT_ETH_MTU_OFFSET 0x02
358
359
#define QUERY_PORT_WIDTH_OFFSET 0x06
359
360
#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
361
+ #define QUERY_PORT_MAC_OFFSET 0x08
360
362
#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
361
363
#define QUERY_PORT_MAX_VL_OFFSET 0x0b
362
364
@@ -367,7 +369,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
367
369
goto out ;
368
370
369
371
MLX4_GET (field , outbox , QUERY_PORT_MTU_OFFSET );
370
- dev_cap -> max_mtu [i ] = field & 0xf ;
372
+ dev_cap -> ib_mtu [i ] = field & 0xf ;
371
373
MLX4_GET (field , outbox , QUERY_PORT_WIDTH_OFFSET );
372
374
dev_cap -> max_port_width [i ] = field & 0xf ;
373
375
MLX4_GET (field , outbox , QUERY_PORT_MAX_GID_PKEY_OFFSET );
@@ -378,7 +380,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
378
380
MLX4_GET (field , outbox , QUERY_PORT_MAX_MACVLAN_OFFSET );
379
381
dev_cap -> log_max_macs [i ] = field & 0xf ;
380
382
dev_cap -> log_max_vlans [i ] = field >> 4 ;
381
-
383
+ MLX4_GET (dev_cap -> eth_mtu [i ], outbox , QUERY_PORT_ETH_MTU_OFFSET );
384
+ MLX4_GET (dev_cap -> def_mac [i ], outbox , QUERY_PORT_MAC_OFFSET );
382
385
}
383
386
}
384
387
@@ -412,7 +415,7 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
412
415
mlx4_dbg (dev , "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n" ,
413
416
dev_cap -> max_cq_sz , dev_cap -> max_qp_sz , dev_cap -> max_srq_sz );
414
417
mlx4_dbg (dev , "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n" ,
415
- dev_cap -> local_ca_ack_delay , 128 << dev_cap -> max_mtu [1 ],
418
+ dev_cap -> local_ca_ack_delay , 128 << dev_cap -> ib_mtu [1 ],
416
419
dev_cap -> max_port_width [1 ]);
417
420
mlx4_dbg (dev , "Max SQ desc size: %d, max SQ S/G: %d\n" ,
418
421
dev_cap -> max_sq_desc_sz , dev_cap -> max_sq_sg );
@@ -824,7 +827,7 @@ int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
824
827
flags |= (dev -> caps .port_width_cap [port ] & 0xf ) << INIT_PORT_PORT_WIDTH_SHIFT ;
825
828
MLX4_PUT (inbox , flags , INIT_PORT_FLAGS_OFFSET );
826
829
827
- field = 128 << dev -> caps .mtu_cap [port ];
830
+ field = 128 << dev -> caps .ib_mtu_cap [port ];
828
831
MLX4_PUT (inbox , field , INIT_PORT_MTU_OFFSET );
829
832
field = dev -> caps .gid_table_len [port ];
830
833
MLX4_PUT (inbox , field , INIT_PORT_MAX_GID_OFFSET );
0 commit comments