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bebarinobebarino
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Merge tag 'clk-imx-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa: - Fix the i.MX8MP clkout1/2 support by using sys_plln_out instead of sys_plln as parents - Add 208 MHz and 416 MHz entries to the PLL1416x - Fix the i.MX93 provider by adding the SPDIF IPG clock - Fix the i.MX93 xcvr DT node clocks by using SPDIF IRP clock instead of BUS_WAKEUP - Filter out LVDS, MIPI DSI, PXP, FLEXIO and MU clocks to i.MX93 only * tag 'clk-imx-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx: Apply some clks only for i.MX93 arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock clk: imx93: Add IMX93_CLK_SPDIF_IPG clock dt-bindings: clock: imx93: Add SPDIF IPG clk clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x clk: imx8mp: Fix clkout1/2 support
2 parents 40384c8 + 48806be commit b7efd22

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5 files changed

+24
-18
lines changed

5 files changed

+24
-18
lines changed

‎arch/arm64/boot/dts/freescale/imx93.dtsi

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -925,7 +925,7 @@
925925
reg-names = "ram", "regs", "rxfifo", "txfifo";
926926
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
927927
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
928-
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
928+
clocks = <&clk IMX93_CLK_SPDIF_IPG>,
929929
<&clk IMX93_CLK_SPDIF_GATE>,
930930
<&clk IMX93_CLK_DUMMY>,
931931
<&clk IMX93_CLK_AUD_XCVR_GATE>;

‎drivers/clk/imx/clk-imx8mp.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -399,8 +399,9 @@ static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_r
399399

400400
static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
401401
"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
402-
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
403-
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
402+
"arm_pll_out", "sys_pll1_out", "sys_pll2_out",
403+
"sys_pll3_out", "dummy", "dummy", "osc_24m",
404+
"dummy", "osc_32k"};
404405

405406
static struct clk_hw **hws;
406407
static struct clk_hw_onecell_data *clk_hw_data;

‎drivers/clk/imx/clk-imx93.c

Lines changed: 17 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515

1616
#include "clk.h"
1717

18-
#define IMX93_CLK_END 207
18+
#define IMX93_CLK_END 208
1919

2020
#define PLAT_IMX93 BIT(0)
2121
#define PLAT_IMX91 BIT(1)
@@ -38,6 +38,7 @@ static u32 share_count_sai2;
3838
static u32 share_count_sai3;
3939
static u32 share_count_mub;
4040
static u32 share_count_pdm;
41+
static u32 share_count_spdif;
4142

4243
static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"};
4344
static const char *parent_names[MAX_SEL][4] = {
@@ -70,8 +71,8 @@ static const struct imx93_clk_root {
7071
{ IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
7172
{ IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
7273
{ IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
73-
{ IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
74-
{ IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, },
74+
{ IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
75+
{ IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, 0, PLAT_IMX93, },
7576
{ IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, },
7677
{ IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, },
7778
{ IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, },
@@ -177,19 +178,19 @@ static const struct imx93_clk_ccgr {
177178
{ IMX93_CLK_WDOG5_GATE, "wdog5", "osc_24m", 0x8400, },
178179
{ IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, },
179180
{ IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, },
180-
{ IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED },
181-
{ IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED },
182-
{ IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub },
183-
{ IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub },
181+
{ IMX93_CLK_MU1_A_GATE, "mu1_a", "bus_aon_root", 0x84c0, CLK_IGNORE_UNUSED, NULL, PLAT_IMX93 },
182+
{ IMX93_CLK_MU2_A_GATE, "mu2_a", "bus_wakeup_root", 0x84c0, CLK_IGNORE_UNUSED, NULL, PLAT_IMX93 },
183+
{ IMX93_CLK_MU1_B_GATE, "mu1_b", "bus_aon_root", 0x8500, 0, &share_count_mub, PLAT_IMX93 },
184+
{ IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub, PLAT_IMX93 },
184185
{ IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, },
185186
{ IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, },
186187
{ IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, },
187188
{ IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, },
188189
{ IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, },
189190
{ IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, },
190191
{ IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, },
191-
{ IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, },
192-
{ IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, },
192+
{ IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, 0, NULL, PLAT_IMX93},
193+
{ IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, 0, NULL, PLAT_IMX93},
193194
{ IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, },
194195
{ IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, },
195196
{ IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, },
@@ -238,10 +239,10 @@ static const struct imx93_clk_ccgr {
238239
{ IMX93_CLK_SAI3_GATE, "sai3", "sai3_root", 0x94c0, 0, &share_count_sai3},
239240
{ IMX93_CLK_SAI3_IPG, "sai3_ipg_clk", "bus_wakeup_root", 0x94c0, 0, &share_count_sai3},
240241
{ IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, },
241-
{ IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, },
242-
{ IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, },
242+
{ IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, 0, NULL, PLAT_IMX93 },
243+
{ IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, 0, NULL, PLAT_IMX93 },
243244
{ IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, },
244-
{ IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, },
245+
{ IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, 0, NULL, PLAT_IMX93 },
245246
{ IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, },
246247
{ IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, },
247248
{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, },
@@ -252,12 +253,13 @@ static const struct imx93_clk_ccgr {
252253
{ IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, },
253254
{ IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, },
254255
{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
255-
{ IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
256+
{ IMX93_CLK_SPDIF_IPG, "spdif_ipg_clk", "bus_wakeup_root", 0x9c00, 0, &share_count_spdif},
257+
{ IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, 0, &share_count_spdif},
256258
{ IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, },
257259
{ IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX93, },
258260
{ IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX93, },
259-
{ IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX91, },
260-
{ IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX91, },
261+
{ IMX91_CLK_ENET2_REGULAR_GATE, "enet2_regular", "wakeup_axi_root", 0x9e00, 0, NULL, PLAT_IMX91, },
262+
{ IMX91_CLK_ENET1_QOS_TSN_GATE, "enet1_qos_tsn", "wakeup_axi_root", 0x9e40, 0, NULL, PLAT_IMX91, },
261263
/* Critical because clk accessed during CPU idle */
262264
{ IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL},
263265
{ IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, },

‎drivers/clk/imx/clk-pll14xx.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
5656
PLL_1416X_RATE(700000000U, 350, 3, 2),
5757
PLL_1416X_RATE(640000000U, 320, 3, 2),
5858
PLL_1416X_RATE(600000000U, 300, 3, 2),
59+
PLL_1416X_RATE(416000000U, 208, 3, 2),
5960
PLL_1416X_RATE(320000000U, 160, 3, 2),
61+
PLL_1416X_RATE(208000000U, 208, 3, 3),
6062
};
6163

6264
static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {

‎include/dt-bindings/clock/imx93-clock.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -209,5 +209,6 @@
209209
#define IMX91_CLK_ENET2_REGULAR 204
210210
#define IMX91_CLK_ENET2_REGULAR_GATE 205
211211
#define IMX91_CLK_ENET1_QOS_TSN_GATE 206
212+
#define IMX93_CLK_SPDIF_IPG 207
212213

213214
#endif

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