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mmc: sdhci-of-at91: introduce driver for the Atmel SDMMC
Introduce driver for he Atmel SDMMC available on sama5d2. It is a sdhci compliant controller. Signed-off-by: Ludovic Desroches <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
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‎Documentation/devicetree/bindings/mmc/sdhci-atmel.txt

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* Atmel SDHCI controller
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This file documents the differences between the core properties in
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Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
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sdhci-of-at91 driver.
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Required properties:
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- compatible: Must be "atmel,sama5d2-sdhci".
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- clocks: Phandlers to the clocks.
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- clock-names: Must be "hclock", "multclk", "baseclk";
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Example:
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sdmmc0: sdio-host@a0000000 {
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compatible = "atmel,sama5d2-sdhci";
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reg = <0xa0000000 0x300>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
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clock-names = "hclock", "multclk", "baseclk";
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};

‎drivers/mmc/host/Kconfig

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@@ -129,6 +129,14 @@ config MMC_SDHCI_OF_ARASAN
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If unsure, say N.
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config MMC_SDHCI_OF_AT91
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tristate "SDHCI OF support for the Atmel SDMMC controller"
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depends on MMC_SDHCI_PLTFM
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depends on OF
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select MMC_SDHCI_IO_ACCESSORS
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help
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This selects the Atmel SDMMC driver
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config MMC_SDHCI_OF_ESDHC
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tristate "SDHCI OF support for the Freescale eSDHC controller"
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depends on MMC_SDHCI_PLTFM

‎drivers/mmc/host/Makefile

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@@ -67,6 +67,7 @@ obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
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obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o
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obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
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obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o
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obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
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obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
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obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
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obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o

‎drivers/mmc/host/sdhci-of-at91.c

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/*
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* Atmel SDMMC controller driver.
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*
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* Copyright (C) 2015 Atmel,
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* 2015 Ludovic Desroches <[email protected]>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "sdhci-pltfm.h"
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#define SDMMC_CACR 0x230
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#define SDMMC_CACR_CAPWREN BIT(0)
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#define SDMMC_CACR_KEY (0x46 << 8)
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struct sdhci_at91_priv {
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struct clk *hclock;
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struct clk *gck;
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struct clk *mainck;
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};
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static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data soc_data_sama5d2 = {
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.ops = &sdhci_at91_sama5d2_ops,
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};
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static const struct of_device_id sdhci_at91_dt_match[] = {
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{ .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 },
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{}
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};
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static int sdhci_at91_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match;
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const struct sdhci_pltfm_data *soc_data;
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_at91_priv *priv;
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unsigned int caps0, caps1;
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unsigned int clk_base, clk_mul;
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unsigned int gck_rate, real_gck_rate;
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int ret;
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match = of_match_device(sdhci_at91_dt_match, &pdev->dev);
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if (!match)
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return -EINVAL;
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soc_data = match->data;
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(&pdev->dev, "unable to allocate private data\n");
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return -ENOMEM;
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}
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priv->mainck = devm_clk_get(&pdev->dev, "baseclk");
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if (IS_ERR(priv->mainck)) {
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dev_err(&pdev->dev, "failed to get baseclk\n");
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return PTR_ERR(priv->mainck);
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}
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priv->hclock = devm_clk_get(&pdev->dev, "hclock");
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if (IS_ERR(priv->hclock)) {
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dev_err(&pdev->dev, "failed to get hclock\n");
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return PTR_ERR(priv->hclock);
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}
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priv->gck = devm_clk_get(&pdev->dev, "multclk");
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if (IS_ERR(priv->gck)) {
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dev_err(&pdev->dev, "failed to get multclk\n");
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return PTR_ERR(priv->gck);
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}
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host = sdhci_pltfm_init(pdev, soc_data, 0);
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if (IS_ERR(host))
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return PTR_ERR(host);
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/*
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* The mult clock is provided by as a generated clock by the PMC
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* controller. In order to set the rate of gck, we have to get the
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* base clock rate and the clock mult from capabilities.
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*/
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clk_prepare_enable(priv->hclock);
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caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES);
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caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1);
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clk_base = (caps0 & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
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clk_mul = (caps1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
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gck_rate = clk_base * 1000000 * (clk_mul + 1);
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ret = clk_set_rate(priv->gck, gck_rate);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to set gck");
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goto hclock_disable_unprepare;
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return -EINVAL;
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}
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/*
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* We need to check if we have the requested rate for gck because in
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* some cases this rate could be not supported. If it happens, the rate
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* is the closest one gck can provide. We have to update the value
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* of clk mul.
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*/
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real_gck_rate = clk_get_rate(priv->gck);
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if (real_gck_rate != gck_rate) {
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clk_mul = real_gck_rate / (clk_base * 1000000) - 1;
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caps1 &= (~SDHCI_CLOCK_MUL_MASK);
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caps1 |= ((clk_mul << SDHCI_CLOCK_MUL_SHIFT) & SDHCI_CLOCK_MUL_MASK);
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/* Set capabilities in r/w mode. */
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writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR);
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writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1);
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/* Set capabilities in ro mode. */
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writel(0, host->ioaddr + SDMMC_CACR);
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dev_info(&pdev->dev, "update clk mul to %u as gck rate is %u Hz\n",
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clk_mul, real_gck_rate);
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}
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clk_prepare_enable(priv->mainck);
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clk_prepare_enable(priv->gck);
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pltfm_host = sdhci_priv(host);
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pltfm_host->priv = priv;
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto clocks_disable_unprepare;
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sdhci_get_of_property(pdev);
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ret = sdhci_add_host(host);
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if (ret)
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goto clocks_disable_unprepare;
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return 0;
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clocks_disable_unprepare:
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clk_disable_unprepare(priv->gck);
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clk_disable_unprepare(priv->mainck);
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hclock_disable_unprepare:
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clk_disable_unprepare(priv->hclock);
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sdhci_pltfm_free(pdev);
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return ret;
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}
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static int sdhci_at91_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_at91_priv *priv = pltfm_host->priv;
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sdhci_pltfm_unregister(pdev);
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clk_disable_unprepare(priv->gck);
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clk_disable_unprepare(priv->hclock);
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clk_disable_unprepare(priv->mainck);
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return 0;
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}
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static struct platform_driver sdhci_at91_driver = {
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.driver = {
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.name = "sdhci-at91",
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.owner = THIS_MODULE,
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.of_match_table = sdhci_at91_dt_match,
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.pm = SDHCI_PLTFM_PMOPS,
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},
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.probe = sdhci_at91_probe,
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.remove = sdhci_at91_remove,
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};
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module_platform_driver(sdhci_at91_driver);
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MODULE_DESCRIPTION("SDHCI driver for at91");
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MODULE_AUTHOR("Ludovic Desroches <[email protected]>");
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MODULE_LICENSE("GPL v2");

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