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Merge tag 'reset-for-4.3' of git://git.pengutronix.de/git/pza/linux into next/drivers
Reset controller changes for v4.3 - moved the DT reset binding includes from include/dt-bindings/reset-controller to include/dt-bindings/reset - new driver for LPC18xx Reset Generation Unit (RGU) - of_device_id array in the STi driver changed to const. - extend SoCFPGA reset driver to support Arria10 - new ath79 reset controller driver for AR71XX/AR9XXX - new driver for Xilinx Zynq reset controller * tag 'reset-for-4.3' of git://git.pengutronix.de/git/pza/linux: reset: reset-zynq: Adding support for Xilinx Zynq reset controller. docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. MIPS: ath79: Add the reset controller to the AR9132 dtsi reset: Add a driver for the reset controller on the AR71XX/AR9XXX devicetree: Add bindings for the ATH79 reset controller reset: socfpga: Update reset-socfpga to read the altr,modrst-offset property doc: dt: add documentation for lpc1850-rgu reset driver reset: add driver for lpc18xx rgu reset: sti: constify of_device_id array ARM: STi: DT: Move reset controller constants into common location MAINTAINERS: add include/dt-bindings/reset path to reset controller entry Signed-off-by: Olof Johansson <[email protected]>
2 parents a005bc6 + 5d44595 commit bd90f11

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lines changed

‎Documentation/devicetree/bindings/reset/ath79-reset.txt

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Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required Properties:
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- compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"
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as fallback
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- reg: Base address and size of the controllers memory area
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- #reset-cells : Specifies the number of cells needed to encode reset
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line, should be 1
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Example:
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reset-controller@1806001c {
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compatible = "qca,ar9132-reset", "qca,ar7100-reset";
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reg = <0x1806001c 0x4>;
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#reset-cells = <1>;
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};

‎Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt

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NXP LPC1850 Reset Generation Unit (RGU)
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========================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "nxp,lpc1850-rgu"
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- reg: register base and length
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- clocks: phandle and clock specifier to RGU clocks
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- clock-names: should contain "delay" and "reg"
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- #reset-cells: should be 1
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See table below for valid peripheral reset numbers. Numbers not
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in the table below are either reserved or not applicable for
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normal operation.
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Reset Peripheral
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9 System control unit (SCU)
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12 ARM Cortex-M0 subsystem core (LPC43xx only)
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13 CPU core
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16 LCD controller
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17 USB0
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18 USB1
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19 DMA
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20 SDIO
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21 External memory controller (EMC)
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22 Ethernet
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25 Flash bank A
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27 EEPROM
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28 GPIO
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29 Flash bank B
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32 Timer0
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33 Timer1
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34 Timer2
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35 Timer3
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36 Repetitive Interrupt timer (RIT)
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37 State Configurable Timer (SCT)
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38 Motor control PWM (MCPWM)
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39 QEI
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40 ADC0
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41 ADC1
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42 DAC
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44 USART0
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45 UART1
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46 USART2
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47 USART3
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48 I2C0
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49 I2C1
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50 SSP0
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51 SSP1
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52 I2S0 and I2S1
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53 Serial Flash Interface (SPIFI)
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54 C_CAN1
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55 C_CAN0
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56 ARM Cortex-M0 application core (LPC4370 only)
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57 SGPIO (LPC43xx only)
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58 SPI (LPC43xx only)
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60 ADCHS (12-bit ADC) (LPC4370 only)
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Refer to NXP LPC18xx or LPC43xx user manual for more details about
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the reset signals and the connected block/peripheral.
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Reset provider example:
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rgu: reset-controller@40053000 {
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compatible = "nxp,lpc1850-rgu";
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reg = <0x40053000 0x1000>;
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clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
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clock-names = "delay", "reg";
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#reset-cells = <1>;
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};
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Reset consumer example:
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mac: ethernet@40010000 {
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compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
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reg = <0x40010000 0x2000>;
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interrupts = <5>;
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interrupt-names = "macirq";
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clocks = <&ccu1 CLK_CPU_ETHERNET>;
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clock-names = "stmmaceth";
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resets = <&rgu 22>;
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reset-names = "stmmaceth";
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status = "disabled";
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};

‎Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt

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};
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Macro definitions for the supported reset channels can be found in:
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include/dt-bindings/reset-controller/stih407-resets.h
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include/dt-bindings/reset/stih407-resets.h

‎Documentation/devicetree/bindings/reset/st,sti-powerdown.txt

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Macro definitions for the supported reset channels can be found in:
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include/dt-bindings/reset-controller/stih415-resets.h
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include/dt-bindings/reset-controller/stih416-resets.h
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include/dt-bindings/reset/stih415-resets.h
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include/dt-bindings/reset/stih416-resets.h

‎Documentation/devicetree/bindings/reset/st,sti-softreset.txt

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Macro definitions for the supported reset channels can be found in:
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include/dt-bindings/reset-controller/stih415-resets.h
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include/dt-bindings/reset-controller/stih416-resets.h
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include/dt-bindings/reset/stih415-resets.h
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include/dt-bindings/reset/stih416-resets.h

‎Documentation/devicetree/bindings/reset/zynq-reset.txt

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Xilinx Zynq Reset Manager
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The Zynq AP-SoC has several different resets.
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See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
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Required properties:
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- compatible: "xlnx,zynq-reset"
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- reg: SLCR offset and size taken via syscon <0x200 0x48>
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- syscon: <&slcr>
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This should be a phandle to the Zynq's SLCR registers.
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- #reset-cells: Must be 1
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The Zynq Reset Manager needs to be a childnode of the SLCR.
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Example:
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rstc: rstc@200 {
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compatible = "xlnx,zynq-reset";
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reg = <0x200 0x48>;
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#reset-cells = <1>;
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syscon = <&slcr>;
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};
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Reset outputs:
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0 : soft reset
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32 : ddr reset
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64 : topsw reset
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96 : dmac reset
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128: usb0 reset
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129: usb1 reset
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160: gem0 reset
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161: gem1 reset
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164: gem0 rx reset
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165: gem1 rx reset
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166: gem0 ref reset
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167: gem1 ref reset
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192: sdio0 reset
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193: sdio1 reset
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196: sdio0 ref reset
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197: sdio1 ref reset
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224: spi0 reset
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225: spi1 reset
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226: spi0 ref reset
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227: spi1 ref reset
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256: can0 reset
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257: can1 reset
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258: can0 ref reset
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259: can1 ref reset
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288: i2c0 reset
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289: i2c1 reset
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320: uart0 reset
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321: uart1 reset
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322: uart0 ref reset
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323: uart1 ref reset
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352: gpio reset
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384: lqspi reset
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385: qspi ref reset
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416: smc reset
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417: smc ref reset
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448: ocm reset
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512: fpga0 out reset
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513: fpga1 out reset
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514: fpga2 out reset
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515: fpga3 out reset
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544: a9 reset 0
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545: a9 reset 1
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552: peri reset
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‎MAINTAINERS

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S: Maintained
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F: drivers/reset/
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F: Documentation/devicetree/bindings/reset/
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F: include/dt-bindings/reset/
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F: include/linux/reset.h
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F: include/linux/reset-controller.h
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‎arch/arm/boot/dts/stih407-family.dtsi

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#include "stih407-pinctrl.dtsi"
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#include <dt-bindings/mfd/st-lpc.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset-controller/stih407-resets.h>
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#include <dt-bindings/reset/stih407-resets.h>
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#include <dt-bindings/interrupt-controller/irq-st.h>
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/ {
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#address-cells = <1>;

‎arch/arm/boot/dts/stih415.dtsi

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#include "stih415-clock.dtsi"
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#include "stih415-pinctrl.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset-controller/stih415-resets.h>
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#include <dt-bindings/reset/stih415-resets.h>
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/ {
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L2: cache-controller {

‎arch/arm/boot/dts/stih416.dtsi

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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset-controller/stih416-resets.h>
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#include <dt-bindings/reset/stih416-resets.h>
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#include <dt-bindings/interrupt-controller/irq-st.h>
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/ {
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L2: cache-controller {

‎arch/mips/Kconfig

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config ATH79
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bool "Atheros AR71XX/AR724X/AR913X based boards"
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select ARCH_HAS_RESET_CONTROLLER
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select ARCH_REQUIRE_GPIOLIB
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select BOOT_RAW
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select CEVT_R4K

‎arch/mips/boot/dts/qca/ar9132.dtsi

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interrupt-controller;
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#interrupt-cells = <1>;
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};
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rst: reset-controller@1806001c {
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compatible = "qca,ar9132-reset",
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"qca,ar7100-reset";
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reg = <0x1806001c 0x4>;
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#reset-cells = <1>;
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};
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};
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spi@1f000000 {

‎drivers/reset/Makefile

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obj-$(CONFIG_RESET_CONTROLLER) += core.o
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obj-$(CONFIG_ARCH_LPC18XX) += reset-lpc18xx.o
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obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
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obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_ARCH_STI) += sti/
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obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
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obj-$(CONFIG_ATH79) += reset-ath79.o

‎drivers/reset/reset-ath79.c

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/*
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* Copyright (C) 2015 Alban Bedel <[email protected]>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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struct ath79_reset {
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struct reset_controller_dev rcdev;
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void __iomem *base;
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spinlock_t lock;
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};
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static int ath79_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct ath79_reset *ath79_reset =
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container_of(rcdev, struct ath79_reset, rcdev);
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&ath79_reset->lock, flags);
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val = readl(ath79_reset->base);
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if (assert)
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val |= BIT(id);
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else
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val &= ~BIT(id);
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writel(val, ath79_reset->base);
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spin_unlock_irqrestore(&ath79_reset->lock, flags);
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return 0;
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}
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static int ath79_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return ath79_reset_update(rcdev, id, true);
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}
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static int ath79_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return ath79_reset_update(rcdev, id, false);
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}
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static int ath79_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct ath79_reset *ath79_reset =
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container_of(rcdev, struct ath79_reset, rcdev);
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u32 val;
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val = readl(ath79_reset->base);
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66+
return !!(val & BIT(id));
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}
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static struct reset_control_ops ath79_reset_ops = {
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.assert = ath79_reset_assert,
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.deassert = ath79_reset_deassert,
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.status = ath79_reset_status,
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};
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static int ath79_reset_probe(struct platform_device *pdev)
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{
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struct ath79_reset *ath79_reset;
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struct resource *res;
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ath79_reset = devm_kzalloc(&pdev->dev,
81+
sizeof(*ath79_reset), GFP_KERNEL);
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if (!ath79_reset)
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return -ENOMEM;
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platform_set_drvdata(pdev, ath79_reset);
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87+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
88+
ath79_reset->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(ath79_reset->base))
90+
return PTR_ERR(ath79_reset->base);
91+
92+
ath79_reset->rcdev.ops = &ath79_reset_ops;
93+
ath79_reset->rcdev.owner = THIS_MODULE;
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ath79_reset->rcdev.of_node = pdev->dev.of_node;
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ath79_reset->rcdev.of_reset_n_cells = 1;
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ath79_reset->rcdev.nr_resets = 32;
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return reset_controller_register(&ath79_reset->rcdev);
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}
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static int ath79_reset_remove(struct platform_device *pdev)
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{
103+
struct ath79_reset *ath79_reset = platform_get_drvdata(pdev);
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reset_controller_unregister(&ath79_reset->rcdev);
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return 0;
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}
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static const struct of_device_id ath79_reset_dt_ids[] = {
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{ .compatible = "qca,ar7100-reset", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ath79_reset_dt_ids);
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static struct platform_driver ath79_reset_driver = {
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.probe = ath79_reset_probe,
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.remove = ath79_reset_remove,
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.driver = {
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.name = "ath79-reset",
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.of_match_table = ath79_reset_dt_ids,
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},
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};
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module_platform_driver(ath79_reset_driver);
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MODULE_AUTHOR("Alban Bedel <[email protected]>");
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MODULE_DESCRIPTION("AR71xx Reset Controller Driver");
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MODULE_LICENSE("GPL");

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