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ilantayariSaeed Mahameed
ilantayari
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Saeed Mahameed
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net/mlx5: Accel, Add IPSec acceleration interface
Add routines for manipulating the hardware IPSec SA database (SADB). In Innova IPSec, a Security Association (SA) is added or deleted via a command message over the SBU connection. The HW then sends a response message over the same connection. Add implementation for Innova IPSec (FPGA-based) hardware. These routines will be used by the IPSec offload support in a later patch However they may also be used by others such as RDMA and RoCE IPSec. mlx5/accel is a middle acceleration layer to allow mlx5e and other ULPs to work directly with mlx5_core rather than Innova FPGA or other mlx5 acceleration providers. In this patchset we add Innova IPSec support and mlx5/accel delegates IPSec offloads to Innova routines. In the future, when IPSec/TLS or any other acceleration gets integrated into ConnectX chip, mlx5/accel layer will provide the integrated acceleration, rather than the Innova one. Signed-off-by: Ilan Tayari <[email protected]> Signed-off-by: Boris Pismenny <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]>
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‎drivers/net/ethernet/mellanox/mlx5/core/Kconfig

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@@ -11,9 +11,13 @@ config MLX5_CORE
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Core driver for low level functionality of the ConnectX-4 and
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Connect-IB cards by Mellanox Technologies.
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config MLX5_ACCEL
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bool
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config MLX5_FPGA
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bool "Mellanox Technologies Innova support"
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depends on MLX5_CORE
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select MLX5_ACCEL
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---help---
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Build support for the Innova family of network cards by Mellanox
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Technologies. Innova network cards are comprised of a ConnectX chip

‎drivers/net/ethernet/mellanox/mlx5/core/Makefile

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@@ -6,7 +6,10 @@ mlx5_core-y := main.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \
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mad.o transobj.o vport.o sriov.o fs_cmd.o fs_core.o \
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fs_counters.o rl.o lag.o dev.o lib/gid.o
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mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o
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mlx5_core-$(CONFIG_MLX5_ACCEL) += accel/ipsec.o
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mlx5_core-$(CONFIG_MLX5_FPGA) += fpga/cmd.o fpga/core.o fpga/conn.o fpga/sdk.o \
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fpga/ipsec.o
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mlx5_core-$(CONFIG_MLX5_CORE_EN) += wq.o eswitch.o eswitch_offloads.o \
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en_main.o en_common.o en_fs.o en_ethtool.o en_tx.o \

‎drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.c

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/*
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* Copyright (c) 2017 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#include <linux/mlx5/device.h>
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#include "accel/ipsec.h"
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#include "mlx5_core.h"
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#include "fpga/ipsec.h"
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void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev,
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struct mlx5_accel_ipsec_sa *cmd)
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{
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if (!MLX5_IPSEC_DEV(mdev))
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return ERR_PTR(-EOPNOTSUPP);
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return mlx5_fpga_ipsec_sa_cmd_exec(mdev, cmd);
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}
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int mlx5_accel_ipsec_sa_cmd_wait(void *ctx)
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{
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return mlx5_fpga_ipsec_sa_cmd_wait(ctx);
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}
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u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev)
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{
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return mlx5_fpga_ipsec_device_caps(mdev);
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}
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unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev)
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{
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return mlx5_fpga_ipsec_counters_count(mdev);
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}
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int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
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unsigned int count)
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{
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return mlx5_fpga_ipsec_counters_read(mdev, counters, count);
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}
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int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev)
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{
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return mlx5_fpga_ipsec_init(mdev);
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}
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void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
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{
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mlx5_fpga_ipsec_cleanup(mdev);
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}

‎drivers/net/ethernet/mellanox/mlx5/core/accel/ipsec.h

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/*
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* Copyright (c) 2017 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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#ifndef __MLX5_ACCEL_IPSEC_H__
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#define __MLX5_ACCEL_IPSEC_H__
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#ifdef CONFIG_MLX5_ACCEL
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#include <linux/mlx5/driver.h>
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enum {
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MLX5_ACCEL_IPSEC_DEVICE = BIT(1),
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MLX5_ACCEL_IPSEC_IPV6 = BIT(2),
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MLX5_ACCEL_IPSEC_ESP = BIT(3),
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MLX5_ACCEL_IPSEC_LSO = BIT(4),
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};
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#define MLX5_IPSEC_SADB_IP_AH BIT(7)
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#define MLX5_IPSEC_SADB_IP_ESP BIT(6)
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#define MLX5_IPSEC_SADB_SA_VALID BIT(5)
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#define MLX5_IPSEC_SADB_SPI_EN BIT(4)
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#define MLX5_IPSEC_SADB_DIR_SX BIT(3)
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#define MLX5_IPSEC_SADB_IPV6 BIT(2)
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enum {
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MLX5_IPSEC_CMD_ADD_SA = 0,
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MLX5_IPSEC_CMD_DEL_SA = 1,
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};
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enum mlx5_accel_ipsec_enc_mode {
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MLX5_IPSEC_SADB_MODE_NONE = 0,
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MLX5_IPSEC_SADB_MODE_AES_GCM_128_AUTH_128 = 1,
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MLX5_IPSEC_SADB_MODE_AES_GCM_256_AUTH_128 = 3,
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};
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#define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \
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MLX5_ACCEL_IPSEC_DEVICE)
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struct mlx5_accel_ipsec_sa {
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__be32 cmd;
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u8 key_enc[32];
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u8 key_auth[32];
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__be32 sip[4];
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__be32 dip[4];
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union {
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struct {
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__be32 reserved;
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u8 salt_iv[8];
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__be32 salt;
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} __packed gcm;
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struct {
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u8 salt[16];
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} __packed cbc;
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};
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__be32 spi;
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__be32 sw_sa_handle;
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__be16 tfclen;
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u8 enc_mode;
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u8 sip_masklen;
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u8 dip_masklen;
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u8 flags;
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u8 reserved[2];
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} __packed;
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/**
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* mlx5_accel_ipsec_sa_cmd_exec - Execute an IPSec SADB command
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* @mdev: mlx5 device
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* @cmd: command to execute
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* May be called from atomic context. Returns context pointer, or error
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* Caller must eventually call mlx5_accel_ipsec_sa_cmd_wait from non-atomic
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* context, to cleanup the context pointer
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*/
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void *mlx5_accel_ipsec_sa_cmd_exec(struct mlx5_core_dev *mdev,
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struct mlx5_accel_ipsec_sa *cmd);
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/**
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* mlx5_accel_ipsec_sa_cmd_wait - Wait for command execution completion
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* @context: Context pointer returned from call to mlx5_accel_ipsec_sa_cmd_exec
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* Sleeps (killable) until command execution is complete.
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* Returns the command result, or -EINTR if killed
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*/
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int mlx5_accel_ipsec_sa_cmd_wait(void *context);
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u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
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unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev);
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int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
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unsigned int count);
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int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev);
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void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev);
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#else
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#define MLX5_IPSEC_DEV(mdev) false
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static inline int mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev)
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{
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return 0;
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}
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static inline void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
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{
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}
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#endif
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#endif /* __MLX5_ACCEL_IPSEC_H__ */

‎drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h

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@@ -51,6 +51,8 @@ struct mlx5_fpga_device {
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struct mlx5_core_mkey mkey;
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struct mlx5_uars_page *uar;
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} conn_res;
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struct mlx5_fpga_ipsec *ipsec;
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};
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#define mlx5_fpga_dbg(__adev, format, ...) \

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