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shijujose4davem330
shijujose4
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davem330
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net: hns3: Add enable and process hw errors from IGU, EGU and NCSI
This patch adds enable and processing of hw errors from IGU(Ingress Unit), EGU(Egress Unit) and NCSI(Network Controller Sideband Interface). Signed-off-by: Shiju Jose <[email protected]> Signed-off-by: Salil Mehta <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -212,6 +212,15 @@ enum hclge_opcode_type {
212212

213213
/* Error INT commands */
214214
HCLGE_COMMON_ECC_INT_CFG = 0x1505,
215+
HCLGE_IGU_EGU_TNL_INT_QUERY = 0x1802,
216+
HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
217+
HCLGE_IGU_EGU_TNL_INT_CLR = 0x1804,
218+
HCLGE_IGU_COMMON_INT_QUERY = 0x1805,
219+
HCLGE_IGU_COMMON_INT_EN = 0x1806,
220+
HCLGE_IGU_COMMON_INT_CLR = 0x1807,
221+
HCLGE_NCSI_INT_QUERY = 0x2400,
222+
HCLGE_NCSI_INT_EN = 0x2401,
223+
HCLGE_NCSI_INT_CLR = 0x2402,
215224
};
216225

217226
#define HCLGE_TQP_REG_OFFSET 0x80000

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

Lines changed: 190 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,30 @@ static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = {
8585
{ /* sentinel */ }
8686
};
8787

88+
static const struct hclge_hw_error hclge_igu_com_err_int[] = {
89+
{ .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err" },
90+
{ .int_msk = BIT(1), .msg = "igu_rx_buf0_ecc_1bit_err" },
91+
{ .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err" },
92+
{ .int_msk = BIT(3), .msg = "igu_rx_buf1_ecc_1bit_err" },
93+
{ /* sentinel */ }
94+
};
95+
96+
static const struct hclge_hw_error hclge_igu_egu_tnl_err_int[] = {
97+
{ .int_msk = BIT(0), .msg = "rx_buf_overflow" },
98+
{ .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow" },
99+
{ .int_msk = BIT(2), .msg = "rx_stp_fifo_undeflow" },
100+
{ .int_msk = BIT(3), .msg = "tx_buf_overflow" },
101+
{ .int_msk = BIT(4), .msg = "tx_buf_underrun" },
102+
{ .int_msk = BIT(5), .msg = "rx_stp_buf_overflow" },
103+
{ /* sentinel */ }
104+
};
105+
106+
static const struct hclge_hw_error hclge_ncsi_err_int[] = {
107+
{ .int_msk = BIT(0), .msg = "ncsi_tx_ecc_1bit_err" },
108+
{ .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err" },
109+
{ /* sentinel */ }
110+
};
111+
88112
static void hclge_log_error(struct device *dev,
89113
const struct hclge_hw_error *err_list,
90114
u32 err_sts)
@@ -229,6 +253,75 @@ static int hclge_enable_common_error(struct hclge_dev *hdev, bool en)
229253
return ret;
230254
}
231255

256+
static int hclge_enable_ncsi_error(struct hclge_dev *hdev, bool en)
257+
{
258+
struct device *dev = &hdev->pdev->dev;
259+
struct hclge_desc desc;
260+
int ret;
261+
262+
if (hdev->pdev->revision < 0x21)
263+
return 0;
264+
265+
/* enable/disable NCSI error interrupts */
266+
hclge_cmd_setup_basic_desc(&desc, HCLGE_NCSI_INT_EN, false);
267+
if (en)
268+
desc.data[0] = cpu_to_le32(HCLGE_NCSI_ERR_INT_EN);
269+
else
270+
desc.data[0] = 0;
271+
272+
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
273+
if (ret)
274+
dev_err(dev,
275+
"failed(%d) to enable/disable NCSI error interrupts\n",
276+
ret);
277+
278+
return ret;
279+
}
280+
281+
static int hclge_enable_igu_egu_error(struct hclge_dev *hdev, bool en)
282+
{
283+
struct device *dev = &hdev->pdev->dev;
284+
struct hclge_desc desc;
285+
int ret;
286+
287+
/* enable/disable error interrupts */
288+
hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_COMMON_INT_EN, false);
289+
if (en)
290+
desc.data[0] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN);
291+
else
292+
desc.data[0] = 0;
293+
desc.data[1] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN_MASK);
294+
295+
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
296+
if (ret) {
297+
dev_err(dev,
298+
"failed(%d) to enable/disable IGU common interrupts\n",
299+
ret);
300+
return ret;
301+
}
302+
303+
hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_EGU_TNL_INT_EN, false);
304+
if (en)
305+
desc.data[0] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN);
306+
else
307+
desc.data[0] = 0;
308+
desc.data[1] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN_MASK);
309+
310+
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
311+
if (ret) {
312+
dev_err(dev,
313+
"failed(%d) to enable/disable IGU-EGU TNL interrupts\n",
314+
ret);
315+
return ret;
316+
}
317+
318+
ret = hclge_enable_ncsi_error(hdev, en);
319+
if (ret)
320+
dev_err(dev, "fail(%d) to en/disable err int\n", ret);
321+
322+
return ret;
323+
}
324+
232325
static void hclge_process_common_error(struct hclge_dev *hdev,
233326
enum hclge_err_int_type type)
234327
{
@@ -285,7 +378,104 @@ static void hclge_process_common_error(struct hclge_dev *hdev,
285378
ret);
286379
}
287380

381+
static void hclge_process_ncsi_error(struct hclge_dev *hdev,
382+
enum hclge_err_int_type type)
383+
{
384+
struct device *dev = &hdev->pdev->dev;
385+
struct hclge_desc desc_rd;
386+
struct hclge_desc desc_wr;
387+
u32 err_sts;
388+
int ret;
389+
390+
if (hdev->pdev->revision < 0x21)
391+
return;
392+
393+
/* read NCSI error status */
394+
ret = hclge_cmd_query_error(hdev, &desc_rd, HCLGE_NCSI_INT_QUERY,
395+
0, 1, HCLGE_NCSI_ERR_INT_TYPE);
396+
if (ret) {
397+
dev_err(dev,
398+
"failed(=%d) to query NCSI error interrupt status\n",
399+
ret);
400+
return;
401+
}
402+
403+
/* log err */
404+
err_sts = le32_to_cpu(desc_rd.data[0]);
405+
hclge_log_error(dev, &hclge_ncsi_err_int[0], err_sts);
406+
407+
/* clear err int */
408+
ret = hclge_cmd_clear_error(hdev, &desc_wr, &desc_rd,
409+
HCLGE_NCSI_INT_CLR, 0);
410+
if (ret)
411+
dev_err(dev, "failed(=%d) to clear NCSI intrerrupt status\n",
412+
ret);
413+
}
414+
415+
static void hclge_process_igu_egu_error(struct hclge_dev *hdev,
416+
enum hclge_err_int_type int_type)
417+
{
418+
struct device *dev = &hdev->pdev->dev;
419+
struct hclge_desc desc_rd;
420+
struct hclge_desc desc_wr;
421+
u32 err_sts;
422+
int ret;
423+
424+
/* read IGU common err sts */
425+
ret = hclge_cmd_query_error(hdev, &desc_rd,
426+
HCLGE_IGU_COMMON_INT_QUERY,
427+
0, 1, int_type);
428+
if (ret) {
429+
dev_err(dev, "failed(=%d) to query IGU common int status\n",
430+
ret);
431+
return;
432+
}
433+
434+
/* log err */
435+
err_sts = le32_to_cpu(desc_rd.data[0]) &
436+
HCLGE_IGU_COM_INT_MASK;
437+
hclge_log_error(dev, &hclge_igu_com_err_int[0], err_sts);
438+
439+
/* clear err int */
440+
ret = hclge_cmd_clear_error(hdev, &desc_wr, &desc_rd,
441+
HCLGE_IGU_COMMON_INT_CLR, 0);
442+
if (ret) {
443+
dev_err(dev, "failed(=%d) to clear IGU common int status\n",
444+
ret);
445+
return;
446+
}
447+
448+
/* read IGU-EGU TNL err sts */
449+
ret = hclge_cmd_query_error(hdev, &desc_rd,
450+
HCLGE_IGU_EGU_TNL_INT_QUERY,
451+
0, 1, int_type);
452+
if (ret) {
453+
dev_err(dev, "failed(=%d) to query IGU-EGU TNL int status\n",
454+
ret);
455+
return;
456+
}
457+
458+
/* log err */
459+
err_sts = le32_to_cpu(desc_rd.data[0]) &
460+
HCLGE_IGU_EGU_TNL_INT_MASK;
461+
hclge_log_error(dev, &hclge_igu_egu_tnl_err_int[0], err_sts);
462+
463+
/* clear err int */
464+
ret = hclge_cmd_clear_error(hdev, &desc_wr, &desc_rd,
465+
HCLGE_IGU_EGU_TNL_INT_CLR, 0);
466+
if (ret) {
467+
dev_err(dev, "failed(=%d) to clear IGU-EGU TNL int status\n",
468+
ret);
469+
return;
470+
}
471+
472+
hclge_process_ncsi_error(hdev, HCLGE_ERR_INT_RAS_NFE);
473+
}
474+
288475
static const struct hclge_hw_blk hw_blk[] = {
476+
{ .msk = BIT(0), .name = "IGU_EGU",
477+
.enable_error = hclge_enable_igu_egu_error,
478+
.process_error = hclge_process_igu_egu_error, },
289479
{ .msk = BIT(5), .name = "COMMON",
290480
.enable_error = hclge_enable_common_error,
291481
.process_error = hclge_process_common_error, },

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,12 @@
2323
#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
2424
#define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
2525
#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
26+
#define HCLGE_IGU_ERR_INT_EN 0x0000066F
27+
#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
28+
#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
29+
#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
30+
#define HCLGE_NCSI_ERR_INT_EN 0x3
31+
#define HCLGE_NCSI_ERR_INT_TYPE 0x9
2632

2733
#define HCLGE_IMP_TCM_ECC_INT_MASK 0xFFFF
2834
#define HCLGE_IMP_ITCM4_ECC_INT_MASK 0x3
@@ -35,6 +41,8 @@
3541
#define HCLGE_CMDQ_NIC_ECC_CLR_MASK 0xFFFF
3642
#define HCLGE_CMDQ_ROCEE_ECC_CLR_MASK 0xFFFF0000
3743
#define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001
44+
#define HCLGE_IGU_COM_INT_MASK 0xF
45+
#define HCLGE_IGU_EGU_TNL_INT_MASK 0x3F
3846

3947
enum hclge_err_int_type {
4048
HCLGE_ERR_INT_MSIX = 0,

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