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Kevin Wangalexdeucher
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drm/amd/swsmu: add aldebaran smu13 ip support (v3)
Add initial swSMU support. v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth) v2: switch to thm/mp v13_0 ip headers (Hawking) v3: squash in updates (Alex) Signed-off-by: Kevin Wang <[email protected]> Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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drivers/gpu/drm/amd/pm/Makefile

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@@ -27,6 +27,7 @@ subdir-ccflags-y += \
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-I$(FULL_AMD_PATH)/pm/swsmu \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu11 \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu12 \
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-I$(FULL_AMD_PATH)/pm/swsmu/smu13 \
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-I$(FULL_AMD_PATH)/pm/powerplay \
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-I$(FULL_AMD_PATH)/pm/powerplay/smumgr\
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-I$(FULL_AMD_PATH)/pm/powerplay/hwmgr
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@@ -0,0 +1,109 @@
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef ALDEBARAN_PP_SMC_H
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#define ALDEBARAN_PP_SMC_H
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#pragma pack(push, 1)
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// SMU Response Codes:
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#define PPSMC_Result_OK 0x1
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#define PPSMC_Result_Failed 0xFF
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#define PPSMC_Result_UnknownCmd 0xFE
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#define PPSMC_Result_CmdRejectedPrereq 0xFD
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#define PPSMC_Result_CmdRejectedBusy 0xFC
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// Message Definitions:
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#define PPSMC_MSG_TestMessage 0x1
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#define PPSMC_MSG_GetSmuVersion 0x2
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#define PPSMC_MSG_Mode1Reset 0x3
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#define PPSMC_MSG_GetDriverIfVersion 0x4
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#define PPSMC_MSG_spare1 0x5
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#define PPSMC_MSG_spare2 0x6
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#define PPSMC_MSG_EnableAllSmuFeatures 0x7
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#define PPSMC_MSG_DisableAllSmuFeatures 0x8
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#define PPSMC_MSG_spare3 0x9
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#define PPSMC_MSG_spare4 0xA
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#define PPSMC_MSG_spare5 0xB
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#define PPSMC_MSG_spare6 0xC
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#define PPSMC_MSG_GetEnabledSmuFeaturesLow 0xD
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#define PPSMC_MSG_GetEnabledSmuFeaturesHigh 0xE
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#define PPSMC_MSG_SetDriverDramAddrHigh 0xF
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#define PPSMC_MSG_SetDriverDramAddrLow 0x10
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#define PPSMC_MSG_SetToolsDramAddrHigh 0x11
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#define PPSMC_MSG_SetToolsDramAddrLow 0x12
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#define PPSMC_MSG_TransferTableSmu2Dram 0x13
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#define PPSMC_MSG_TransferTableDram2Smu 0x14
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#define PPSMC_MSG_UseDefaultPPTable 0x15
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#define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x16
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#define PPSMC_MSG_SetSystemVirtualDramAddrLow 0x17
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#define PPSMC_MSG_SetSoftMinByFreq 0x18
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#define PPSMC_MSG_SetSoftMaxByFreq 0x19
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#define PPSMC_MSG_SetHardMinByFreq 0x1A
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#define PPSMC_MSG_SetHardMaxByFreq 0x1B
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#define PPSMC_MSG_GetMinDpmFreq 0x1C
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#define PPSMC_MSG_GetMaxDpmFreq 0x1D
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#define PPSMC_MSG_GetDpmFreqByIndex 0x1E
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#define PPSMC_MSG_SetWorkloadMask 0x1F
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#define PPSMC_MSG_GetVoltageByDpm 0x20
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#define PPSMC_MSG_GetVoltageByDpmOverdrive 0x21
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#define PPSMC_MSG_SetPptLimit 0x22
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#define PPSMC_MSG_GetPptLimit 0x23
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#define PPSMC_MSG_PrepareMp1ForUnload 0x24
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#define PPSMC_MSG_PrepareMp1ForReset 0x25
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#define PPSMC_MSG_SoftReset 0x26
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#define PPSMC_MSG_RunDcBtc 0x27
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#define PPSMC_MSG_DramLogSetDramAddrHigh 0x28
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#define PPSMC_MSG_DramLogSetDramAddrLow 0x29
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#define PPSMC_MSG_DramLogSetDramSize 0x2A
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#define PPSMC_MSG_GetDebugData 0x2B
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#define PPSMC_MSG_WaflTest 0x2C
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#define PPSMC_MSG_spare7 0x2D
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#define PPSMC_MSG_SetMemoryChannelEnable 0x2E
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#define PPSMC_MSG_SetNumBadHbmPagesRetired 0x2F
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#define PPSMC_MSG_DFCstateControl 0x32
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#define PPSMC_MSG_GetGmiPwrDnHyst 0x33
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#define PPSMC_MSG_SetGmiPwrDnHyst 0x34
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#define PPSMC_MSG_GmiPwrDnControl 0x35
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#define PPSMC_MSG_EnterGfxoff 0x36
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#define PPSMC_MSG_ExitGfxoff 0x37
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#define PPSMC_MSG_SetExecuteDMATest 0x38
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#define PPSMC_MSG_EnableDeterminism 0x39
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#define PPSMC_MSG_DisableDeterminism 0x3A
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#define PPSMC_MSG_SetUclkDpmMode 0x3B
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#define PPSMC_Message_Count 0x3C
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typedef enum {
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GFXOFF_ERROR_NO_ERROR,
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GFXOFF_ERROR_DISALLOWED,
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GFXOFF_ERROR_GFX_BUSY,
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GFXOFF_ERROR_GFX_OFF,
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GFXOFF_ERROR_GFX_ON,
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} GFXOFF_ERROR_e;
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typedef uint32_t PPSMC_Result;
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typedef uint32_t PPSMC_Msg;
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#pragma pack(pop)
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#endif

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

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@@ -1286,6 +1286,7 @@ extern const struct amd_ip_funcs smu_ip_funcs;
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extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
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extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
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extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
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bool is_support_sw_smu(struct amdgpu_device *adev);
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bool is_support_cclk_dpm(struct amdgpu_device *adev);

drivers/gpu/drm/amd/pm/inc/smu_types.h

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@@ -168,9 +168,16 @@
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__SMU_DUMMY_MAP(PowerGateAtHub), \
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__SMU_DUMMY_MAP(SetSoftMinJpeg), \
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__SMU_DUMMY_MAP(SetHardMinFclkByFreq), \
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__SMU_DUMMY_MAP(DFCstateControl), \
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__SMU_DUMMY_MAP(GmiPwrDnControl), \
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__SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE),\
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__SMU_DUMMY_MAP(DFCstateControl), \
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__SMU_DUMMY_MAP(GmiPwrDnControl), \
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__SMU_DUMMY_MAP(spare), \
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__SMU_DUMMY_MAP(SetNumBadHbmPagesRetired), \
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__SMU_DUMMY_MAP(GetGmiPwrDnHyst), \
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__SMU_DUMMY_MAP(SetGmiPwrDnHyst), \
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__SMU_DUMMY_MAP(EnterGfxoff), \
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__SMU_DUMMY_MAP(ExitGfxoff), \
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__SMU_DUMMY_MAP(SetExecuteDMATest), \
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__SMU_DUMMY_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE), \
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__SMU_DUMMY_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE), \
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__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH), \
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__SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \
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__SMU_DUMMY_MAP(SetSlowPPTLimit), \
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__SMU_DUMMY_MAP(GetFastPPTLimit), \
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__SMU_DUMMY_MAP(GetSlowPPTLimit), \
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__SMU_DUMMY_MAP(EnableDeterminism), \
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__SMU_DUMMY_MAP(DisableDeterminism), \
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__SMU_DUMMY_MAP(SetUclkDpmMode), \
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#undef __SMU_DUMMY_MAP
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#define __SMU_DUMMY_MAP(type) SMU_MSG_##type
@@ -239,6 +249,7 @@ enum smu_clk_type {
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SMU_SCLK,
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SMU_MCLK,
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SMU_PCIE,
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SMU_LCLK,
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SMU_OD_CCLK,
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SMU_OD_SCLK,
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SMU_OD_MCLK,
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__SMU_DUMMY_MAP(DPM_SOCCLK), \
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__SMU_DUMMY_MAP(DPM_UVD), \
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__SMU_DUMMY_MAP(DPM_VCE), \
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__SMU_DUMMY_MAP(DPM_LCLK), \
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__SMU_DUMMY_MAP(ULV), \
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__SMU_DUMMY_MAP(DPM_MP0CLK), \
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__SMU_DUMMY_MAP(DPM_LINK), \
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__SMU_DUMMY_MAP(DS_MP1CLK), \
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__SMU_DUMMY_MAP(DS_MP0CLK), \
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__SMU_DUMMY_MAP(XGMI), \
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__SMU_DUMMY_MAP(XGMI_PER_LINK_PWR_DWN), \
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__SMU_DUMMY_MAP(DPM_GFX_PACE), \
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__SMU_DUMMY_MAP(MEM_VDDCI_SCALING), \
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__SMU_DUMMY_MAP(MEM_MVDD_SCALING), \
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__SMU_DUMMY_MAP(MMHUB_PG), \
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__SMU_DUMMY_MAP(ATHUB_PG), \
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__SMU_DUMMY_MAP(APCC_DFLL), \
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__SMU_DUMMY_MAP(DF_CSTATE), \
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__SMU_DUMMY_MAP(DPM_GFX_GPO), \
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__SMU_DUMMY_MAP(WAFL_CG), \
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__SMU_DUMMY_MAP(CCLK_DPM), \
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__SMU_DUMMY_MAP(ISP_DPM), \
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__SMU_DUMMY_MAP(A55_DPM), \
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__SMU_DUMMY_MAP(CVIP_DSP_DPM), \
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__SMU_DUMMY_MAP(MSMU_LOW_POWER),
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__SMU_DUMMY_MAP(MSMU_LOW_POWER), \
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__SMU_DUMMY_MAP(FUSE_CG), \
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__SMU_DUMMY_MAP(MP1_CG), \
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__SMU_DUMMY_MAP(SMUIO_CG), \
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__SMU_DUMMY_MAP(THM_CG), \
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__SMU_DUMMY_MAP(CLK_CG), \
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#undef __SMU_DUMMY_MAP
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#define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT

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