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torvaldstorvalds
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: arch/m68knommu/platform/68360/commproc.c: Checkpatch cleanup arch/m68knommu/mm/fault.c: Checkpatch cleanup m68knommu: improve short help of m68knommu/Kconfig/RAMSIZE for '0' case m68knommu: remove un-used mcfsmc.h m68knommu: add smc91x support for ColdFire NETtel boards m68knommu: add smc91x support to ColdFire 5249 platform m68knommu: remove size limit on non-MMU TASK_SIZE m68knommu: fix broken use of BUAD_TABLE_SIZE in 68328serial driver m68knommu: Coldfire QSPI platform support
2 parents 99765cc + 724b62b commit c19eb8f

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20 files changed

+1226
-262
lines changed

20 files changed

+1226
-262
lines changed

‎arch/m68k/include/asm/m520xsim.h

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@@ -113,6 +113,7 @@
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#define MCF_GPIO_PAR_UART (0xA4036)
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#define MCF_GPIO_PAR_FECI2C (0xA4033)
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#define MCF_GPIO_PAR_QSPI (0xA4034)
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#define MCF_GPIO_PAR_FEC (0xA4038)
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#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)

‎arch/m68k/include/asm/m523xsim.h

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@@ -127,5 +127,10 @@
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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130+
/*
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* Pin Assignment
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*/
133+
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
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#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
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/****************************************************************************/
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#endif /* m523xsim_h */

‎arch/m68k/include/asm/m5249sim.h

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@@ -69,10 +69,12 @@
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#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */
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#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
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#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
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#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_QSPI 28 /* QSPI, Level 4 */
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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‎arch/m68k/include/asm/m527xsim.h

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@@ -31,6 +31,7 @@
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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#define MCFINT_UART1 14 /* Interrupt number for UART1 */
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#define MCFINT_UART2 15 /* Interrupt number for UART2 */
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#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
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#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */
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/*
@@ -120,6 +121,9 @@
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#define MCFGPIO_PIN_MAX 100
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
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#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
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#endif
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#ifdef CONFIG_M5275
@@ -212,6 +216,8 @@
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#define MCFGPIO_PIN_MAX 148
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
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#endif
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/*
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#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
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/*
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* GPIO pins setups to enable the UARTs.
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*/

‎arch/m68k/include/asm/m528xsim.h

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@@ -29,6 +29,7 @@
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#define MCFINT_VECBASE 64 /* Vector base number */
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#define MCFINT_UART0 13 /* Interrupt number for UART0 */
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#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
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#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
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/*
@@ -249,70 +250,4 @@
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#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
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/*********************************************************************
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*
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* Queued Serial Peripheral Interface (QSPI) Module
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*
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*********************************************************************/
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/* Derek - 21 Feb 2005 */
259-
/* change to the format used in I2C */
260-
/* Read/Write access macros for general use */
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#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340
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#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344
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#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348
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#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C
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#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350
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#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354
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#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354
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/* Bit level definitions and macros */
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#define MCF5282_QSPI_QMR_MSTR (0x8000)
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#define MCF5282_QSPI_QMR_DOHIE (0x4000)
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#define MCF5282_QSPI_QMR_BITS_16 (0x0000)
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#define MCF5282_QSPI_QMR_BITS_8 (0x2000)
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#define MCF5282_QSPI_QMR_BITS_9 (0x2400)
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#define MCF5282_QSPI_QMR_BITS_10 (0x2800)
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#define MCF5282_QSPI_QMR_BITS_11 (0x2C00)
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#define MCF5282_QSPI_QMR_BITS_12 (0x3000)
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#define MCF5282_QSPI_QMR_BITS_13 (0x3400)
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#define MCF5282_QSPI_QMR_BITS_14 (0x3800)
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#define MCF5282_QSPI_QMR_BITS_15 (0x3C00)
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#define MCF5282_QSPI_QMR_CPOL (0x0200)
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#define MCF5282_QSPI_QMR_CPHA (0x0100)
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#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF))
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#define MCF5282_QSPI_QDLYR_SPE (0x80)
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#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
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#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
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#define MCF5282_QSPI_QWR_HALT (0x8000)
290-
#define MCF5282_QSPI_QWR_WREN (0x4000)
291-
#define MCF5282_QSPI_QWR_WRTO (0x2000)
292-
#define MCF5282_QSPI_QWR_CSIV (0x1000)
293-
#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
294-
#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
295-
#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F))
296-
297-
#define MCF5282_QSPI_QIR_WCEFB (0x8000)
298-
#define MCF5282_QSPI_QIR_ABRTB (0x4000)
299-
#define MCF5282_QSPI_QIR_ABRTL (0x1000)
300-
#define MCF5282_QSPI_QIR_WCEFE (0x0800)
301-
#define MCF5282_QSPI_QIR_ABRTE (0x0400)
302-
#define MCF5282_QSPI_QIR_SPIFE (0x0100)
303-
#define MCF5282_QSPI_QIR_WCEF (0x0008)
304-
#define MCF5282_QSPI_QIR_ABRT (0x0004)
305-
#define MCF5282_QSPI_QIR_SPIF (0x0001)
306-
307-
#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F))
308-
309-
#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00))
310-
#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8)
311-
#define MCF5282_QSPI_QCR_CONT (0x8000)
312-
#define MCF5282_QSPI_QCR_BITSE (0x4000)
313-
#define MCF5282_QSPI_QCR_DT (0x2000)
314-
#define MCF5282_QSPI_QCR_DSCK (0x1000)
315-
#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8)
316-
317-
/****************************************************************************/
318253
#endif /* m528xsim_h */

‎arch/m68k/include/asm/m532xsim.h

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@@ -17,6 +17,7 @@
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#define MCFINT_UART0 26 /* Interrupt number for UART0 */
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#define MCFINT_UART1 27 /* Interrupt number for UART1 */
1919
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
20+
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
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2122
#define MCF_WTM_WCR MCF_REG16(0xFC098000)
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‎arch/m68k/include/asm/mcfqspi.h

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/*
2+
* Definitions for Freescale Coldfire QSPI module
3+
*
4+
* Copyright 2010 Steven King <[email protected]>
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*
6+
* This program is free software; you can redistribute it and/or modify
7+
* it under the terms of the GNU General Public License version 2
8+
* as published by the Free Software Foundation.
9+
*
10+
* This program is distributed in the hope that it will be useful,
11+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
12+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13+
* GNU General Public License for more details.
14+
*
15+
* You should have received a copy of the GNU General Public License along
16+
* with this program; if not, write to the Free Software Foundation, Inc.,
17+
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
18+
*
19+
*/
20+
21+
#ifndef mcfqspi_h
22+
#define mcfqspi_h
23+
24+
#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
25+
#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
26+
#elif defined(CONFIG_M5249)
27+
#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
28+
#elif defined(CONFIG_M520x) || defined(CONFIG_M532x)
29+
#define MCFQSPI_IOBASE 0xFC058000
30+
#endif
31+
#define MCFQSPI_IOSIZE 0x40
32+
33+
/**
34+
* struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
35+
* @setup: setup the control; allocate gpio's, etc. May be NULL.
36+
* @teardown: finish with the control; free gpio's, etc. May be NULL.
37+
* @select: output the signals to select the device. Can not be NULL.
38+
* @deselect: output the signals to deselect the device. Can not be NULL.
39+
*
40+
* The QSPI module has 4 hardware chip selects. We don't use them. Instead
41+
* platforms are required to supply a mcfqspi_cs_control as a part of the
42+
* platform data for each QSPI master controller. Only the select and
43+
* deselect functions are required.
44+
*/
45+
struct mcfqspi_cs_control {
46+
int (*setup)(struct mcfqspi_cs_control *);
47+
void (*teardown)(struct mcfqspi_cs_control *);
48+
void (*select)(struct mcfqspi_cs_control *, u8, bool);
49+
void (*deselect)(struct mcfqspi_cs_control *, u8, bool);
50+
};
51+
52+
/**
53+
* struct mcfqspi_platform_data - platform data for the coldfire qspi driver
54+
* @bus_num: board specific identifier for this qspi driver.
55+
* @num_chipselects: number of chip selects supported by this qspi driver.
56+
* @cs_control: platform dependent chip select control.
57+
*/
58+
struct mcfqspi_platform_data {
59+
s16 bus_num;
60+
u16 num_chipselect;
61+
struct mcfqspi_cs_control *cs_control;
62+
};
63+
64+
#endif /* mcfqspi_h */

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