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torvaldstorvalds
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Merge tag 'drm-next-2022-01-21' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Thanks to Daniel for taking care of things while I was out, just a set of merge window fixes that came in this week, two i915 display fixes and a bunch of misc amdgpu, along with a radeon regression fix. amdgpu: - SR-IOV fix - VCN harvest fix - Suspend/resume fixes - Tahiti fix - Enable GPU recovery on yellow carp radeon: - Fix error handling regression in radeon_driver_open_kms i915: - Update EHL display voltage swing table - Fix programming the ADL-P display TC voltage swing" * tag 'drm-next-2022-01-21' of git://anongit.freedesktop.org/drm/drm: drm/radeon: fix error handling in radeon_driver_open_kms drm/amd/amdgpu: fixing read wrong pf2vf data in SRIOV drm/amdgpu: apply vcn harvest quirk drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequence drm/i915/display/ehl: Update voltage swing table drm/amd/display: Revert W/A for hard hangs on DCN20/DCN21 drm/amdgpu: drop flags check for CHIP_IP_DISCOVERY drm/amdgpu: Fix rejecting Tahiti GPUs drm/amdgpu: don't do resets on APUs which don't support it drm/amdgpu: invert the logic in amdgpu_device_should_recover_gpu() drm/amdgpu: Enable recovery on yellow carp
2 parents 39e77c4 + ccf3458 commit c2c94b3

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18 files changed

+108
-146
lines changed

18 files changed

+108
-146
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 18 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2354,7 +2354,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
23542354
}
23552355

23562356
if (amdgpu_sriov_vf(adev))
2357-
amdgpu_virt_exchange_data(adev);
2357+
amdgpu_virt_init_data_exchange(adev);
23582358

23592359
r = amdgpu_ib_pool_init(adev);
23602360
if (r) {
@@ -4450,33 +4450,24 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
44504450

44514451
if (amdgpu_gpu_recovery == -1) {
44524452
switch (adev->asic_type) {
4453-
case CHIP_BONAIRE:
4454-
case CHIP_HAWAII:
4455-
case CHIP_TOPAZ:
4456-
case CHIP_TONGA:
4457-
case CHIP_FIJI:
4458-
case CHIP_POLARIS10:
4459-
case CHIP_POLARIS11:
4460-
case CHIP_POLARIS12:
4461-
case CHIP_VEGAM:
4462-
case CHIP_VEGA20:
4463-
case CHIP_VEGA10:
4464-
case CHIP_VEGA12:
4465-
case CHIP_RAVEN:
4466-
case CHIP_ARCTURUS:
4467-
case CHIP_RENOIR:
4468-
case CHIP_NAVI10:
4469-
case CHIP_NAVI14:
4470-
case CHIP_NAVI12:
4471-
case CHIP_SIENNA_CICHLID:
4472-
case CHIP_NAVY_FLOUNDER:
4473-
case CHIP_DIMGREY_CAVEFISH:
4474-
case CHIP_BEIGE_GOBY:
4475-
case CHIP_VANGOGH:
4476-
case CHIP_ALDEBARAN:
4477-
break;
4478-
default:
4453+
#ifdef CONFIG_DRM_AMDGPU_SI
4454+
case CHIP_VERDE:
4455+
case CHIP_TAHITI:
4456+
case CHIP_PITCAIRN:
4457+
case CHIP_OLAND:
4458+
case CHIP_HAINAN:
4459+
#endif
4460+
#ifdef CONFIG_DRM_AMDGPU_CIK
4461+
case CHIP_KAVERI:
4462+
case CHIP_KABINI:
4463+
case CHIP_MULLINS:
4464+
#endif
4465+
case CHIP_CARRIZO:
4466+
case CHIP_STONEY:
4467+
case CHIP_CYAN_SKILLFISH:
44794468
goto disabled;
4469+
default:
4470+
break;
44804471
}
44814472
}
44824473

‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

Lines changed: 27 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -243,6 +243,30 @@ static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary)
243243
return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE);
244244
}
245245

246+
static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev)
247+
{
248+
/*
249+
* So far, apply this quirk only on those Navy Flounder boards which
250+
* have a bad harvest table of VCN config.
251+
*/
252+
if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
253+
(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) {
254+
switch (adev->pdev->revision) {
255+
case 0xC1:
256+
case 0xC2:
257+
case 0xC3:
258+
case 0xC5:
259+
case 0xC7:
260+
case 0xCF:
261+
case 0xDF:
262+
adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
263+
break;
264+
default:
265+
break;
266+
}
267+
}
268+
}
269+
246270
static int amdgpu_discovery_init(struct amdgpu_device *adev)
247271
{
248272
struct table_info *info;
@@ -548,11 +572,9 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
548572
break;
549573
}
550574
}
551-
/* some IP discovery tables on Navy Flounder don't have this set correctly */
552-
if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) &&
553-
(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2)) &&
554-
(adev->pdev->revision != 0xFF))
555-
adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
575+
576+
amdgpu_discovery_harvest_config_quirk(adev);
577+
556578
if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
557579
adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
558580
adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1930,11 +1930,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
19301930
return -ENODEV;
19311931
}
19321932

1933-
if (flags == 0) {
1934-
DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n");
1935-
return -ENODEV;
1936-
}
1937-
19381933
if (amdgpu_virtual_display ||
19391934
amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
19401935
supports_atomic = true;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

Lines changed: 7 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -625,20 +625,20 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
625625
adev->virt.fw_reserve.p_vf2pf = NULL;
626626
adev->virt.vf2pf_update_interval_ms = 0;
627627

628-
if (adev->bios != NULL) {
629-
adev->virt.vf2pf_update_interval_ms = 2000;
628+
if (adev->mman.fw_vram_usage_va != NULL) {
629+
/* go through this logic in ip_init and reset to init workqueue*/
630+
amdgpu_virt_exchange_data(adev);
630631

632+
INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
633+
schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
634+
} else if (adev->bios != NULL) {
635+
/* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/
631636
adev->virt.fw_reserve.p_pf2vf =
632637
(struct amd_sriov_msg_pf2vf_info_header *)
633638
(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
634639

635640
amdgpu_virt_read_pf2vf_data(adev);
636641
}
637-
638-
if (adev->virt.vf2pf_update_interval_ms != 0) {
639-
INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item);
640-
schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms));
641-
}
642642
}
643643

644644

@@ -674,12 +674,6 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev)
674674
if (adev->virt.ras_init_done)
675675
amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
676676
}
677-
} else if (adev->bios != NULL) {
678-
adev->virt.fw_reserve.p_pf2vf =
679-
(struct amd_sriov_msg_pf2vf_info_header *)
680-
(adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
681-
682-
amdgpu_virt_read_pf2vf_data(adev);
683677
}
684678
}
685679

‎drivers/gpu/drm/amd/amdgpu/cik.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1428,6 +1428,10 @@ static int cik_asic_reset(struct amdgpu_device *adev)
14281428
{
14291429
int r;
14301430

1431+
/* APUs don't have full asic reset */
1432+
if (adev->flags & AMD_IS_APU)
1433+
return 0;
1434+
14311435
if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
14321436
dev_info(adev->dev, "BACO reset\n");
14331437
r = amdgpu_dpm_baco_reset(adev);

‎drivers/gpu/drm/amd/amdgpu/vi.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -956,6 +956,10 @@ static int vi_asic_reset(struct amdgpu_device *adev)
956956
{
957957
int r;
958958

959+
/* APUs don't have full asic reset */
960+
if (adev->flags & AMD_IS_APU)
961+
return 0;
962+
959963
if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
960964
dev_info(adev->dev, "BACO reset\n");
961965
r = amdgpu_dpm_baco_reset(adev);

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,6 @@
3838
#include "clk/clk_11_0_0_offset.h"
3939
#include "clk/clk_11_0_0_sh_mask.h"
4040

41-
#include "irq/dcn20/irq_service_dcn20.h"
4241

4342
#undef FN
4443
#define FN(reg_name, field_name) \
@@ -223,8 +222,6 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
223222
bool force_reset = false;
224223
bool p_state_change_support;
225224
int total_plane_count;
226-
int irq_src;
227-
uint32_t hpd_state;
228225

229226
if (dc->work_arounds.skip_clock_update)
230227
return;
@@ -242,13 +239,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
242239
if (dc->res_pool->pp_smu)
243240
pp_smu = &dc->res_pool->pp_smu->nv_funcs;
244241

245-
for (irq_src = DC_IRQ_SOURCE_HPD1; irq_src <= DC_IRQ_SOURCE_HPD6; irq_src++) {
246-
hpd_state = dc_get_hpd_state_dcn20(dc->res_pool->irqs, irq_src);
247-
if (hpd_state)
248-
break;
249-
}
250-
251-
if (display_count == 0 && !hpd_state)
242+
if (display_count == 0)
252243
enter_display_off = true;
253244

254245
if (enter_display_off == safe_to_lower) {

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,6 @@
4242
#include "clk/clk_10_0_2_sh_mask.h"
4343
#include "renoir_ip_offset.h"
4444

45-
#include "irq/dcn21/irq_service_dcn21.h"
4645

4746
/* Constants */
4847

@@ -129,11 +128,9 @@ static void rn_update_clocks(struct clk_mgr *clk_mgr_base,
129128
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
130129
struct dc *dc = clk_mgr_base->ctx->dc;
131130
int display_count;
132-
int irq_src;
133131
bool update_dppclk = false;
134132
bool update_dispclk = false;
135133
bool dpp_clock_lowered = false;
136-
uint32_t hpd_state;
137134

138135
struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
139136

@@ -150,14 +147,8 @@ static void rn_update_clocks(struct clk_mgr *clk_mgr_base,
150147

151148
display_count = rn_get_active_display_cnt_wa(dc, context);
152149

153-
for (irq_src = DC_IRQ_SOURCE_HPD1; irq_src <= DC_IRQ_SOURCE_HPD5; irq_src++) {
154-
hpd_state = dc_get_hpd_state_dcn21(dc->res_pool->irqs, irq_src);
155-
if (hpd_state)
156-
break;
157-
}
158-
159150
/* if we can go lower, go lower */
160-
if (display_count == 0 && !hpd_state) {
151+
if (display_count == 0) {
161152
rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER);
162153
/* update power state */
163154
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;

‎drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -132,31 +132,6 @@ enum dc_irq_source to_dal_irq_source_dcn20(
132132
}
133133
}
134134

135-
uint32_t dc_get_hpd_state_dcn20(struct irq_service *irq_service, enum dc_irq_source source)
136-
{
137-
const struct irq_source_info *info;
138-
uint32_t addr;
139-
uint32_t value;
140-
uint32_t current_status;
141-
142-
info = find_irq_source_info(irq_service, source);
143-
if (!info)
144-
return 0;
145-
146-
addr = info->status_reg;
147-
if (!addr)
148-
return 0;
149-
150-
value = dm_read_reg(irq_service->ctx, addr);
151-
current_status =
152-
get_reg_field_value(
153-
value,
154-
HPD0_DC_HPD_INT_STATUS,
155-
DC_HPD_SENSE);
156-
157-
return current_status;
158-
}
159-
160135
static bool hpd_ack(
161136
struct irq_service *irq_service,
162137
const struct irq_source_info *info)

‎drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,4 @@
3131
struct irq_service *dal_irq_service_dcn20_create(
3232
struct irq_service_init_data *init_data);
3333

34-
uint32_t dc_get_hpd_state_dcn20(struct irq_service *irq_service, enum dc_irq_source source);
35-
3634
#endif

‎drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

Lines changed: 0 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -134,31 +134,6 @@ static enum dc_irq_source to_dal_irq_source_dcn21(struct irq_service *irq_servic
134134
return DC_IRQ_SOURCE_INVALID;
135135
}
136136

137-
uint32_t dc_get_hpd_state_dcn21(struct irq_service *irq_service, enum dc_irq_source source)
138-
{
139-
const struct irq_source_info *info;
140-
uint32_t addr;
141-
uint32_t value;
142-
uint32_t current_status;
143-
144-
info = find_irq_source_info(irq_service, source);
145-
if (!info)
146-
return 0;
147-
148-
addr = info->status_reg;
149-
if (!addr)
150-
return 0;
151-
152-
value = dm_read_reg(irq_service->ctx, addr);
153-
current_status =
154-
get_reg_field_value(
155-
value,
156-
HPD0_DC_HPD_INT_STATUS,
157-
DC_HPD_SENSE);
158-
159-
return current_status;
160-
}
161-
162137
static bool hpd_ack(
163138
struct irq_service *irq_service,
164139
const struct irq_source_info *info)

‎drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,4 @@
3131
struct irq_service *dal_irq_service_dcn21_create(
3232
struct irq_service_init_data *init_data);
3333

34-
uint32_t dc_get_hpd_state_dcn21(struct irq_service *irq_service, enum dc_irq_source source);
35-
3634
#endif

‎drivers/gpu/drm/amd/display/dc/irq/irq_service.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,7 +79,7 @@ void dal_irq_service_destroy(struct irq_service **irq_service)
7979
*irq_service = NULL;
8080
}
8181

82-
const struct irq_source_info *find_irq_source_info(
82+
static const struct irq_source_info *find_irq_source_info(
8383
struct irq_service *irq_service,
8484
enum dc_irq_source source)
8585
{

‎drivers/gpu/drm/amd/display/dc/irq/irq_service.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -69,10 +69,6 @@ struct irq_service {
6969
const struct irq_service_funcs *funcs;
7070
};
7171

72-
const struct irq_source_info *find_irq_source_info(
73-
struct irq_service *irq_service,
74-
enum dc_irq_source source);
75-
7672
void dal_irq_service_construct(
7773
struct irq_service *irq_service,
7874
struct irq_service_init_data *init_data);

‎drivers/gpu/drm/i915/display/intel_ddi.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1298,6 +1298,28 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
12981298

12991299
intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
13001300
DKL_TX_DP20BITMODE, 0);
1301+
1302+
if (IS_ALDERLAKE_P(dev_priv)) {
1303+
u32 val;
1304+
1305+
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1306+
if (ln == 0) {
1307+
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1308+
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1309+
} else {
1310+
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1311+
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1312+
}
1313+
} else {
1314+
val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1315+
val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1316+
}
1317+
1318+
intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
1319+
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1320+
DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1321+
val);
1322+
}
13011323
}
13021324
}
13031325

‎drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -477,14 +477,14 @@ static const struct intel_ddi_buf_trans icl_combo_phy_trans_hdmi = {
477477
static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_dp[] = {
478478
/* NT mV Trans mV db */
479479
{ .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
480-
{ .icl = { 0xA, 0x47, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */
481-
{ .icl = { 0xC, 0x64, 0x34, 0x00, 0x0B } }, /* 350 700 6.0 */
482-
{ .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 350 900 8.2 */
480+
{ .icl = { 0xA, 0x47, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
481+
{ .icl = { 0xC, 0x64, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */
482+
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 350 900 8.2 */
483483
{ .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
484-
{ .icl = { 0xC, 0x64, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */
484+
{ .icl = { 0xC, 0x64, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
485485
{ .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
486486
{ .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
487-
{ .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */
487+
{ .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */
488488
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
489489
};
490490

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