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hbruecknerMartin Schwidefsky
hbrueckner
authored and
Martin Schwidefsky
committed
s390/cpum_cf: Export event names in sysfs
Provide PMU event attributes for supported counters and export their symbolic names to the sysfs "events" directory. See the /sys/devices/cpum_cf/events/ directory for a list of available counters. Note that you might require counter set authorizations for the LPAR to use them. Signed-off-by: Hendrik Brueckner <[email protected]> Signed-off-by: Martin Schwidefsky <[email protected]>
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‎arch/s390/include/asm/perf_event.h

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,18 @@
11
/*
22
* Performance event support - s390 specific definitions.
33
*
4-
* Copyright IBM Corp. 2009, 2012
4+
* Copyright IBM Corp. 2009, 2013
55
* Author(s): Martin Schwidefsky <[email protected]>
66
* Hendrik Brueckner <[email protected]>
77
*/
88

9+
#ifndef _ASM_S390_PERF_EVENT_H
10+
#define _ASM_S390_PERF_EVENT_H
11+
12+
#ifdef CONFIG_64BIT
13+
14+
#include <linux/perf_event.h>
15+
#include <linux/device.h>
916
#include <asm/cpu_mf.h>
1017

1118
/* CPU-measurement counter facility */
@@ -15,7 +22,18 @@
1522
#define PMU_F_RESERVED 0x1000
1623
#define PMU_F_ENABLED 0x2000
1724

18-
#ifdef CONFIG_64BIT
25+
/* Perf defintions for PMU event attributes in sysfs */
26+
extern __init const struct attribute_group **cpumf_cf_event_group(void);
27+
extern ssize_t cpumf_events_sysfs_show(struct device *dev,
28+
struct device_attribute *attr,
29+
char *page);
30+
#define EVENT_VAR(_cat, _name) event_attr_##_cat##_##_name
31+
#define EVENT_PTR(_cat, _name) (&EVENT_VAR(_cat, _name).attr.attr)
32+
33+
#define CPUMF_EVENT_ATTR(cat, name, id) \
34+
PMU_EVENT_ATTR(name, EVENT_VAR(cat, name), id, cpumf_events_sysfs_show)
35+
#define CPUMF_EVENT_PTR(cat, name) EVENT_PTR(cat, name)
36+
1937

2038
/* Perf callbacks */
2139
struct pt_regs;
@@ -24,3 +42,4 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs);
2442
#define perf_misc_flags(regs) perf_misc_flags(regs)
2543

2644
#endif /* CONFIG_64BIT */
45+
#endif /* _ASM_S390_PERF_EVENT_H */

‎arch/s390/kernel/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,8 @@ obj-$(CONFIG_FTRACE_SYSCALLS) += ftrace.o
6060
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
6161

6262
ifdef CONFIG_64BIT
63-
obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_cpum_cf.o
63+
obj-$(CONFIG_PERF_EVENTS) += perf_event.o perf_cpum_cf.o \
64+
perf_cpum_cf_events.o
6465
obj-y += runtime_instr.o cache.o
6566
endif
6667

‎arch/s390/kernel/perf_cpum_cf.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -680,6 +680,7 @@ static int __init cpumf_pmu_init(void)
680680
goto out;
681681
}
682682

683+
cpumf_pmu.attr_groups = cpumf_cf_event_group();
683684
rc = perf_pmu_register(&cpumf_pmu, "cpum_cf", PERF_TYPE_RAW);
684685
if (rc) {
685686
pr_err("Registering the cpum_cf PMU failed with rc=%i\n", rc);

‎arch/s390/kernel/perf_cpum_cf_events.c

Lines changed: 322 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,322 @@
1+
/*
2+
* Perf PMU sysfs events attributes for available CPU-measurement counters
3+
*
4+
*/
5+
6+
#include <linux/slab.h>
7+
#include <linux/perf_event.h>
8+
9+
10+
/* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
11+
12+
CPUMF_EVENT_ATTR(cf, CPU_CYCLES, 0x0000);
13+
CPUMF_EVENT_ATTR(cf, INSTRUCTIONS, 0x0001);
14+
CPUMF_EVENT_ATTR(cf, L1I_DIR_WRITES, 0x0002);
15+
CPUMF_EVENT_ATTR(cf, L1I_PENALTY_CYCLES, 0x0003);
16+
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_CPU_CYCLES, 0x0020);
17+
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
18+
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
19+
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
20+
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
21+
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
22+
CPUMF_EVENT_ATTR(cf, L1D_DIR_WRITES, 0x0004);
23+
CPUMF_EVENT_ATTR(cf, L1D_PENALTY_CYCLES, 0x0005);
24+
CPUMF_EVENT_ATTR(cf, PRNG_FUNCTIONS, 0x0040);
25+
CPUMF_EVENT_ATTR(cf, PRNG_CYCLES, 0x0041);
26+
CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_FUNCTIONS, 0x0042);
27+
CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_CYCLES, 0x0043);
28+
CPUMF_EVENT_ATTR(cf, SHA_FUNCTIONS, 0x0044);
29+
CPUMF_EVENT_ATTR(cf, SHA_CYCLES, 0x0045);
30+
CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_FUNCTIONS, 0x0046);
31+
CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_CYCLES, 0x0047);
32+
CPUMF_EVENT_ATTR(cf, DEA_FUNCTIONS, 0x0048);
33+
CPUMF_EVENT_ATTR(cf, DEA_CYCLES, 0x0049);
34+
CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_FUNCTIONS, 0x004a);
35+
CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_CYCLES, 0x004b);
36+
CPUMF_EVENT_ATTR(cf, AES_FUNCTIONS, 0x004c);
37+
CPUMF_EVENT_ATTR(cf, AES_CYCLES, 0x004d);
38+
CPUMF_EVENT_ATTR(cf, AES_BLOCKED_FUNCTIONS, 0x004e);
39+
CPUMF_EVENT_ATTR(cf, AES_BLOCKED_CYCLES, 0x004f);
40+
CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
41+
CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
42+
CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
43+
CPUMF_EVENT_ATTR(cf_z10, L1D_L3_LOCAL_WRITES, 0x0083);
44+
CPUMF_EVENT_ATTR(cf_z10, L1I_L3_REMOTE_WRITES, 0x0084);
45+
CPUMF_EVENT_ATTR(cf_z10, L1D_L3_REMOTE_WRITES, 0x0085);
46+
CPUMF_EVENT_ATTR(cf_z10, L1D_LMEM_SOURCED_WRITES, 0x0086);
47+
CPUMF_EVENT_ATTR(cf_z10, L1I_LMEM_SOURCED_WRITES, 0x0087);
48+
CPUMF_EVENT_ATTR(cf_z10, L1D_RO_EXCL_WRITES, 0x0088);
49+
CPUMF_EVENT_ATTR(cf_z10, L1I_CACHELINE_INVALIDATES, 0x0089);
50+
CPUMF_EVENT_ATTR(cf_z10, ITLB1_WRITES, 0x008a);
51+
CPUMF_EVENT_ATTR(cf_z10, DTLB1_WRITES, 0x008b);
52+
CPUMF_EVENT_ATTR(cf_z10, TLB2_PTE_WRITES, 0x008c);
53+
CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_WRITES, 0x008d);
54+
CPUMF_EVENT_ATTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
55+
CPUMF_EVENT_ATTR(cf_z10, ITLB1_MISSES, 0x0091);
56+
CPUMF_EVENT_ATTR(cf_z10, DTLB1_MISSES, 0x0092);
57+
CPUMF_EVENT_ATTR(cf_z10, L2C_STORES_SENT, 0x0093);
58+
CPUMF_EVENT_ATTR(cf_z196, L1D_L2_SOURCED_WRITES, 0x0080);
59+
CPUMF_EVENT_ATTR(cf_z196, L1I_L2_SOURCED_WRITES, 0x0081);
60+
CPUMF_EVENT_ATTR(cf_z196, DTLB1_MISSES, 0x0082);
61+
CPUMF_EVENT_ATTR(cf_z196, ITLB1_MISSES, 0x0083);
62+
CPUMF_EVENT_ATTR(cf_z196, L2C_STORES_SENT, 0x0085);
63+
CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0086);
64+
CPUMF_EVENT_ATTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0087);
65+
CPUMF_EVENT_ATTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES, 0x0088);
66+
CPUMF_EVENT_ATTR(cf_z196, L1D_RO_EXCL_WRITES, 0x0089);
67+
CPUMF_EVENT_ATTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x008a);
68+
CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x008b);
69+
CPUMF_EVENT_ATTR(cf_z196, DTLB1_HPAGE_WRITES, 0x008c);
70+
CPUMF_EVENT_ATTR(cf_z196, L1D_LMEM_SOURCED_WRITES, 0x008d);
71+
CPUMF_EVENT_ATTR(cf_z196, L1I_LMEM_SOURCED_WRITES, 0x008e);
72+
CPUMF_EVENT_ATTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x008f);
73+
CPUMF_EVENT_ATTR(cf_z196, DTLB1_WRITES, 0x0090);
74+
CPUMF_EVENT_ATTR(cf_z196, ITLB1_WRITES, 0x0091);
75+
CPUMF_EVENT_ATTR(cf_z196, TLB2_PTE_WRITES, 0x0092);
76+
CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES, 0x0093);
77+
CPUMF_EVENT_ATTR(cf_z196, TLB2_CRSTE_WRITES, 0x0094);
78+
CPUMF_EVENT_ATTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0096);
79+
CPUMF_EVENT_ATTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0098);
80+
CPUMF_EVENT_ATTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
81+
CPUMF_EVENT_ATTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009b);
82+
CPUMF_EVENT_ATTR(cf_zec12, DTLB1_MISSES, 0x0080);
83+
CPUMF_EVENT_ATTR(cf_zec12, ITLB1_MISSES, 0x0081);
84+
CPUMF_EVENT_ATTR(cf_zec12, L1D_L2I_SOURCED_WRITES, 0x0082);
85+
CPUMF_EVENT_ATTR(cf_zec12, L1I_L2I_SOURCED_WRITES, 0x0083);
86+
CPUMF_EVENT_ATTR(cf_zec12, L1D_L2D_SOURCED_WRITES, 0x0084);
87+
CPUMF_EVENT_ATTR(cf_zec12, DTLB1_WRITES, 0x0085);
88+
CPUMF_EVENT_ATTR(cf_zec12, L1D_LMEM_SOURCED_WRITES, 0x0087);
89+
CPUMF_EVENT_ATTR(cf_zec12, L1I_LMEM_SOURCED_WRITES, 0x0089);
90+
CPUMF_EVENT_ATTR(cf_zec12, L1D_RO_EXCL_WRITES, 0x008a);
91+
CPUMF_EVENT_ATTR(cf_zec12, DTLB1_HPAGE_WRITES, 0x008b);
92+
CPUMF_EVENT_ATTR(cf_zec12, ITLB1_WRITES, 0x008c);
93+
CPUMF_EVENT_ATTR(cf_zec12, TLB2_PTE_WRITES, 0x008d);
94+
CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES, 0x008e);
95+
CPUMF_EVENT_ATTR(cf_zec12, TLB2_CRSTE_WRITES, 0x008f);
96+
CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
97+
CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES, 0x0091);
98+
CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES, 0x0092);
99+
CPUMF_EVENT_ATTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES, 0x0093);
100+
CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES, 0x0094);
101+
CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TEND, 0x0095);
102+
CPUMF_EVENT_ATTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0096);
103+
CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV, 0x0097);
104+
CPUMF_EVENT_ATTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV, 0x0098);
105+
CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES, 0x0099);
106+
CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES, 0x009a);
107+
CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES, 0x009b);
108+
CPUMF_EVENT_ATTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES, 0x009c);
109+
CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES, 0x009d);
110+
CPUMF_EVENT_ATTR(cf_zec12, TX_C_TEND, 0x009e);
111+
CPUMF_EVENT_ATTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x009f);
112+
CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV, 0x00a0);
113+
CPUMF_EVENT_ATTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV, 0x00a1);
114+
CPUMF_EVENT_ATTR(cf_zec12, TX_NC_TABORT, 0x00b1);
115+
CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_NO_SPECIAL, 0x00b2);
116+
CPUMF_EVENT_ATTR(cf_zec12, TX_C_TABORT_SPECIAL, 0x00b3);
117+
118+
static struct attribute *cpumcf_pmu_event_attr[] = {
119+
CPUMF_EVENT_PTR(cf, CPU_CYCLES),
120+
CPUMF_EVENT_PTR(cf, INSTRUCTIONS),
121+
CPUMF_EVENT_PTR(cf, L1I_DIR_WRITES),
122+
CPUMF_EVENT_PTR(cf, L1I_PENALTY_CYCLES),
123+
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_CPU_CYCLES),
124+
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_INSTRUCTIONS),
125+
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_DIR_WRITES),
126+
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES),
127+
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_DIR_WRITES),
128+
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES),
129+
CPUMF_EVENT_PTR(cf, L1D_DIR_WRITES),
130+
CPUMF_EVENT_PTR(cf, L1D_PENALTY_CYCLES),
131+
CPUMF_EVENT_PTR(cf, PRNG_FUNCTIONS),
132+
CPUMF_EVENT_PTR(cf, PRNG_CYCLES),
133+
CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_FUNCTIONS),
134+
CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_CYCLES),
135+
CPUMF_EVENT_PTR(cf, SHA_FUNCTIONS),
136+
CPUMF_EVENT_PTR(cf, SHA_CYCLES),
137+
CPUMF_EVENT_PTR(cf, SHA_BLOCKED_FUNCTIONS),
138+
CPUMF_EVENT_PTR(cf, SHA_BLOCKED_CYCLES),
139+
CPUMF_EVENT_PTR(cf, DEA_FUNCTIONS),
140+
CPUMF_EVENT_PTR(cf, DEA_CYCLES),
141+
CPUMF_EVENT_PTR(cf, DEA_BLOCKED_FUNCTIONS),
142+
CPUMF_EVENT_PTR(cf, DEA_BLOCKED_CYCLES),
143+
CPUMF_EVENT_PTR(cf, AES_FUNCTIONS),
144+
CPUMF_EVENT_PTR(cf, AES_CYCLES),
145+
CPUMF_EVENT_PTR(cf, AES_BLOCKED_FUNCTIONS),
146+
CPUMF_EVENT_PTR(cf, AES_BLOCKED_CYCLES),
147+
NULL,
148+
};
149+
150+
static struct attribute *cpumcf_z10_pmu_event_attr[] __initdata = {
151+
CPUMF_EVENT_PTR(cf_z10, L1I_L2_SOURCED_WRITES),
152+
CPUMF_EVENT_PTR(cf_z10, L1D_L2_SOURCED_WRITES),
153+
CPUMF_EVENT_PTR(cf_z10, L1I_L3_LOCAL_WRITES),
154+
CPUMF_EVENT_PTR(cf_z10, L1D_L3_LOCAL_WRITES),
155+
CPUMF_EVENT_PTR(cf_z10, L1I_L3_REMOTE_WRITES),
156+
CPUMF_EVENT_PTR(cf_z10, L1D_L3_REMOTE_WRITES),
157+
CPUMF_EVENT_PTR(cf_z10, L1D_LMEM_SOURCED_WRITES),
158+
CPUMF_EVENT_PTR(cf_z10, L1I_LMEM_SOURCED_WRITES),
159+
CPUMF_EVENT_PTR(cf_z10, L1D_RO_EXCL_WRITES),
160+
CPUMF_EVENT_PTR(cf_z10, L1I_CACHELINE_INVALIDATES),
161+
CPUMF_EVENT_PTR(cf_z10, ITLB1_WRITES),
162+
CPUMF_EVENT_PTR(cf_z10, DTLB1_WRITES),
163+
CPUMF_EVENT_PTR(cf_z10, TLB2_PTE_WRITES),
164+
CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_WRITES),
165+
CPUMF_EVENT_PTR(cf_z10, TLB2_CRSTE_HPAGE_WRITES),
166+
CPUMF_EVENT_PTR(cf_z10, ITLB1_MISSES),
167+
CPUMF_EVENT_PTR(cf_z10, DTLB1_MISSES),
168+
CPUMF_EVENT_PTR(cf_z10, L2C_STORES_SENT),
169+
NULL,
170+
};
171+
172+
static struct attribute *cpumcf_z196_pmu_event_attr[] __initdata = {
173+
CPUMF_EVENT_PTR(cf_z196, L1D_L2_SOURCED_WRITES),
174+
CPUMF_EVENT_PTR(cf_z196, L1I_L2_SOURCED_WRITES),
175+
CPUMF_EVENT_PTR(cf_z196, DTLB1_MISSES),
176+
CPUMF_EVENT_PTR(cf_z196, ITLB1_MISSES),
177+
CPUMF_EVENT_PTR(cf_z196, L2C_STORES_SENT),
178+
CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L3_SOURCED_WRITES),
179+
CPUMF_EVENT_PTR(cf_z196, L1D_ONBOOK_L4_SOURCED_WRITES),
180+
CPUMF_EVENT_PTR(cf_z196, L1I_ONBOOK_L4_SOURCED_WRITES),
181+
CPUMF_EVENT_PTR(cf_z196, L1D_RO_EXCL_WRITES),
182+
CPUMF_EVENT_PTR(cf_z196, L1D_OFFBOOK_L4_SOURCED_WRITES),
183+
CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L4_SOURCED_WRITES),
184+
CPUMF_EVENT_PTR(cf_z196, DTLB1_HPAGE_WRITES),
185+
CPUMF_EVENT_PTR(cf_z196, L1D_LMEM_SOURCED_WRITES),
186+
CPUMF_EVENT_PTR(cf_z196, L1I_LMEM_SOURCED_WRITES),
187+
CPUMF_EVENT_PTR(cf_z196, L1I_OFFBOOK_L3_SOURCED_WRITES),
188+
CPUMF_EVENT_PTR(cf_z196, DTLB1_WRITES),
189+
CPUMF_EVENT_PTR(cf_z196, ITLB1_WRITES),
190+
CPUMF_EVENT_PTR(cf_z196, TLB2_PTE_WRITES),
191+
CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_HPAGE_WRITES),
192+
CPUMF_EVENT_PTR(cf_z196, TLB2_CRSTE_WRITES),
193+
CPUMF_EVENT_PTR(cf_z196, L1D_ONCHIP_L3_SOURCED_WRITES),
194+
CPUMF_EVENT_PTR(cf_z196, L1D_OFFCHIP_L3_SOURCED_WRITES),
195+
CPUMF_EVENT_PTR(cf_z196, L1I_ONCHIP_L3_SOURCED_WRITES),
196+
CPUMF_EVENT_PTR(cf_z196, L1I_OFFCHIP_L3_SOURCED_WRITES),
197+
NULL,
198+
};
199+
200+
static struct attribute *cpumcf_zec12_pmu_event_attr[] __initdata = {
201+
CPUMF_EVENT_PTR(cf_zec12, DTLB1_MISSES),
202+
CPUMF_EVENT_PTR(cf_zec12, ITLB1_MISSES),
203+
CPUMF_EVENT_PTR(cf_zec12, L1D_L2I_SOURCED_WRITES),
204+
CPUMF_EVENT_PTR(cf_zec12, L1I_L2I_SOURCED_WRITES),
205+
CPUMF_EVENT_PTR(cf_zec12, L1D_L2D_SOURCED_WRITES),
206+
CPUMF_EVENT_PTR(cf_zec12, DTLB1_WRITES),
207+
CPUMF_EVENT_PTR(cf_zec12, L1D_LMEM_SOURCED_WRITES),
208+
CPUMF_EVENT_PTR(cf_zec12, L1I_LMEM_SOURCED_WRITES),
209+
CPUMF_EVENT_PTR(cf_zec12, L1D_RO_EXCL_WRITES),
210+
CPUMF_EVENT_PTR(cf_zec12, DTLB1_HPAGE_WRITES),
211+
CPUMF_EVENT_PTR(cf_zec12, ITLB1_WRITES),
212+
CPUMF_EVENT_PTR(cf_zec12, TLB2_PTE_WRITES),
213+
CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_HPAGE_WRITES),
214+
CPUMF_EVENT_PTR(cf_zec12, TLB2_CRSTE_WRITES),
215+
CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES),
216+
CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_zec12, L1D_ONBOOK_L4_SOURCED_WRITES),
219+
CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L4_SOURCED_WRITES),
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CPUMF_EVENT_PTR(cf_zec12, TX_NC_TEND),
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CPUMF_EVENT_PTR(cf_zec12, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_zec12, L1D_OFFCHIP_L3_SOURCED_WRITES_IV),
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CPUMF_EVENT_PTR(cf_zec12, L1D_OFFBOOK_L3_SOURCED_WRITES_IV),
224+
CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES),
225+
CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES),
226+
CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES),
227+
CPUMF_EVENT_PTR(cf_zec12, L1I_ONBOOK_L4_SOURCED_WRITES),
228+
CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L4_SOURCED_WRITES),
229+
CPUMF_EVENT_PTR(cf_zec12, TX_C_TEND),
230+
CPUMF_EVENT_PTR(cf_zec12, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
231+
CPUMF_EVENT_PTR(cf_zec12, L1I_OFFCHIP_L3_SOURCED_WRITES_IV),
232+
CPUMF_EVENT_PTR(cf_zec12, L1I_OFFBOOK_L3_SOURCED_WRITES_IV),
233+
CPUMF_EVENT_PTR(cf_zec12, TX_NC_TABORT),
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CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_NO_SPECIAL),
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CPUMF_EVENT_PTR(cf_zec12, TX_C_TABORT_SPECIAL),
236+
NULL,
237+
};
238+
239+
/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
240+
241+
static struct attribute_group cpumsf_pmu_events_group = {
242+
.name = "events",
243+
.attrs = cpumcf_pmu_event_attr,
244+
};
245+
246+
PMU_FORMAT_ATTR(event, "config:0-63");
247+
248+
static struct attribute *cpumsf_pmu_format_attr[] = {
249+
&format_attr_event.attr,
250+
NULL,
251+
};
252+
253+
static struct attribute_group cpumsf_pmu_format_group = {
254+
.name = "format",
255+
.attrs = cpumsf_pmu_format_attr,
256+
};
257+
258+
static const struct attribute_group *cpumsf_pmu_attr_groups[] = {
259+
&cpumsf_pmu_events_group,
260+
&cpumsf_pmu_format_group,
261+
NULL,
262+
};
263+
264+
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static __init struct attribute **merge_attr(struct attribute **a,
266+
struct attribute **b)
267+
{
268+
struct attribute **new;
269+
int j, i;
270+
271+
for (j = 0; a[j]; j++)
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;
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for (i = 0; b[i]; i++)
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j++;
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j++;
276+
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new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
278+
if (!new)
279+
return NULL;
280+
j = 0;
281+
for (i = 0; a[i]; i++)
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new[j++] = a[i];
283+
for (i = 0; b[i]; i++)
284+
new[j++] = b[i];
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new[j] = NULL;
286+
287+
return new;
288+
}
289+
290+
__init const struct attribute_group **cpumf_cf_event_group(void)
291+
{
292+
struct attribute **combined, **model;
293+
struct cpuid cpu_id;
294+
295+
get_cpu_id(&cpu_id);
296+
switch (cpu_id.machine) {
297+
case 0x2097:
298+
case 0x2098:
299+
model = cpumcf_z10_pmu_event_attr;
300+
break;
301+
case 0x2817:
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case 0x2818:
303+
model = cpumcf_z196_pmu_event_attr;
304+
break;
305+
case 0x2827:
306+
case 0x2828:
307+
model = cpumcf_zec12_pmu_event_attr;
308+
break;
309+
default:
310+
model = NULL;
311+
break;
312+
};
313+
314+
if (!model)
315+
goto out;
316+
317+
combined = merge_attr(cpumcf_pmu_event_attr, model);
318+
if (combined)
319+
cpumsf_pmu_events_group.attrs = combined;
320+
out:
321+
return cpumsf_pmu_attr_groups;
322+
}

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