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YueHaibingdavem330
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liquidio: remove redundant function cn23xx_dump_iq_regs
There are no in-tree callers of cn23xx_dump_iq_regs. Signed-off-by: YueHaibing <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c

Lines changed: 0 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1417,50 +1417,6 @@ int validate_cn23xx_pf_config_info(struct octeon_device *oct,
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return 0;
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}
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1420-
void cn23xx_dump_iq_regs(struct octeon_device *oct)
1421-
{
1422-
u32 regval, q_no;
1423-
1424-
dev_dbg(&oct->pci_dev->dev, "SLI_IQ_DOORBELL_0 [0x%x]: 0x%016llx\n",
1425-
CN23XX_SLI_IQ_DOORBELL(0),
1426-
CVM_CAST64(octeon_read_csr64
1427-
(oct, CN23XX_SLI_IQ_DOORBELL(0))));
1428-
1429-
dev_dbg(&oct->pci_dev->dev, "SLI_IQ_BASEADDR_0 [0x%x]: 0x%016llx\n",
1430-
CN23XX_SLI_IQ_BASE_ADDR64(0),
1431-
CVM_CAST64(octeon_read_csr64
1432-
(oct, CN23XX_SLI_IQ_BASE_ADDR64(0))));
1433-
1434-
dev_dbg(&oct->pci_dev->dev, "SLI_IQ_FIFO_RSIZE_0 [0x%x]: 0x%016llx\n",
1435-
CN23XX_SLI_IQ_SIZE(0),
1436-
CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_IQ_SIZE(0))));
1437-
1438-
dev_dbg(&oct->pci_dev->dev, "SLI_CTL_STATUS [0x%x]: 0x%016llx\n",
1439-
CN23XX_SLI_CTL_STATUS,
1440-
CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_CTL_STATUS)));
1441-
1442-
for (q_no = 0; q_no < CN23XX_MAX_INPUT_QUEUES; q_no++) {
1443-
dev_dbg(&oct->pci_dev->dev, "SLI_PKT[%d]_INPUT_CTL [0x%x]: 0x%016llx\n",
1444-
q_no, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
1445-
CVM_CAST64(octeon_read_csr64
1446-
(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no))));
1447-
}
1448-
1449-
pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);
1450-
dev_dbg(&oct->pci_dev->dev, "Config DevCtl [0x%x]: 0x%08x\n",
1451-
CN23XX_CONFIG_PCIE_DEVCTL, regval);
1452-
1453-
dev_dbg(&oct->pci_dev->dev, "SLI_PRT[%d]_CFG [0x%llx]: 0x%016llx\n",
1454-
oct->pcie_port, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port),
1455-
CVM_CAST64(lio_pci_readq(
1456-
oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port))));
1457-
1458-
dev_dbg(&oct->pci_dev->dev, "SLI_S2M_PORT[%d]_CTL [0x%x]: 0x%016llx\n",
1459-
oct->pcie_port, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port),
1460-
CVM_CAST64(octeon_read_csr64(
1461-
oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port))));
1462-
}
1463-
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int cn23xx_fw_loaded(struct octeon_device *oct)
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{
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u64 val;

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