PCI: pciehp: Add quirk to handle spurious DLLSC on a x4x4 SSD

When an Intel P5608 SSD is bifurcated into x4x4 mode, and the upstream
ports both support hotplugging on each respective x4 device, a slot
management system for the SSD requires both x4 slots to have power
removed via sysfs (echo 0 > slot/N/power), from the OS before it can
safely turn-off physical power for the whole x8 device. The implications
are that slot status will display powered off and link inactive statuses
for the x4 devices where the devices are actually powered until both
ports have powered off.

The issue with the SSD manifests when power is removed from the
first-half and then the second-half. During the first-half removal, slot
status shows the slot as powered-down and link-inactive, while internal
power and link remain active while waiting for the second-half to have
power removed. When power is then removed from the second-half, the
first-half starts shutdown sequence and will trigger a DLLSC event. This
is misinterpreted as an enabling event and causes the first-half to be
re-enabled.

The spurious enable can be resolved by ignoring link status change
events when no link is active when in the off state. This patch adds a
quirk for specific P5608 SSDs which have been tested for compatibility.

Signed-off-by: Jon Derrick <[email protected]>
Signed-off-by: James Puthukattukaran <[email protected]>

Orabug: 34358322

Signed-off-by: Thomas Tai <[email protected]>
Reviewed-by: John Donnelly  <[email protected]>
Reviewed-by: Jack Vogel <[email protected]>
Reviewed-by: Henry Willard <[email protected]>
(cherry picked from commit ee7633b0ca00aca2bc4f9c7632fe5abb88a9bb7e)
Signed-off-by: Jack Vogel <[email protected]>

Author: thomastaioracle

drivers/pci/hotplug/pciehp_ctrl.c

@@ -225,6 +225,7 @@ void pciehp_handle_disable_request(struct controller *ctrl)
 void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events)
 {
 	int present, link_active;
+        struct pci_dev *pdev = ctrl->pcie->port;
 
 	/*
 	 * If the slot is on and presence or link has changed, turn it off.
@@ -265,6 +266,13 @@ void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events)
 		cancel_delayed_work(&ctrl->button_work);
 		fallthrough;
 	case OFF_STATE:
+		/* Look at comment for quirk_shared_slot function */
+		if (pdev->shared_pcc_and_link_slot &&
+			(events & PCI_EXP_SLTSTA_DLLSC) && !link_active) {
+			mutex_unlock(&ctrl->state_lock);
+			pdev->shared_pcc_and_link_slot = false;
+			break;
+		}
 		ctrl->state = POWERON_STATE;
 		mutex_unlock(&ctrl->state_lock);
 		if (present)

drivers/pci/quirks.c

@@ -5821,3 +5821,37 @@ static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
 	pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
+
+#ifdef CONFIG_HOTPLUG_PCI_PCIE
+/*
+ * This is an Intel NVMe SSD which sits in a x8 pciehp slot but is bifurcated
+ * as a x4x4 and manifests as two slots with respect to PCIe hot plug register
+ * states. However, the hotplug controller treats these slots as a single x8
+ * slot for link and power. Either one of the two slots can be powered down
+ * separately and the slot status will show negative power and link states, but
+ * internal power and link will be active until the last of the two slots is
+ * powered down. When the last of the two x4 slots is turned off, power and
+ * link will be turned off for the x8 slot by the HP controller. This
+ * configuration causes some interesting behavior in bringup sequence
+ *
+ * When the second slot is powered off to remove the card, this will cause the
+ * link to go down for both x4 slots. So, the x4 that is already powered down
+ * earlier will see a DLLSC event and attempt to bring itself up (card present,
+ * link change event, link state is down). Special handling is required in
+ * pciehp_handle_presence_or_link_change to prevent this unintended bring up
+ */
+static void quirk_shared_pcc_and_link_slot(struct pci_dev *pdev)
+{
+	struct pci_dev *parent = pci_upstream_bridge(pdev);
+
+	if (parent && pdev->subsystem_vendor == 0x108e) {
+	switch (pdev->subsystem_device) {
+		/* P5608 */
+		case 0x487d:
+		case 0x488d:
+			parent->shared_pcc_and_link_slot = 1;
+		}
+	}
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0b60, quirk_shared_pcc_and_link_slot);
+#endif /* CONFIG_HOTPLUG_PCI_PCIE */

include/linux/pci.h

@@ -340,6 +340,9 @@ struct pci_dev {
 	u8		msi_cap;	/* MSI capability offset */
 	u8		msix_cap;	/* MSI-X capability offset */
 	u8		pcie_mpss:3;	/* PCIe Max Payload Size Supported */
+#ifdef CONFIG_HOTPLUG_PCI_PCIE
+	UEK_KABI_FILL_HOLE(u8 shared_pcc_and_link_slot:1) /* two "slots" sharing link/power */
+#endif
 	u8		rom_base_reg;	/* Config register controlling ROM */
 	u8		pin;		/* Interrupt pin this device uses */
 	u16		pcie_flags_reg;	/* Cached PCIe Capabilities Register */