Skip to content

Commit c93fc28

Browse files
torvaldstorvalds
committed
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: MIPS: csrc-r4k: Fix declaration depending on the wrong CONFIG_ symbol. MIPS: csrc-r4k: Fix spelling mistake. MIPS: RB532: Provide functions for gpio configuration MIPS: IP22: Make indy_sc_ops variable static MIPS: RB532: GPIO register offsets are relative to GPIOBASE MIPS: Malta: Fix include paths in malta-amon.c
2 parents e3b4ae7 + a24e849 commit c93fc28

File tree

8 files changed

+90
-133
lines changed

8 files changed

+90
-133
lines changed

‎arch/mips/include/asm/mach-rc32434/gpio.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,5 +84,7 @@ extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned
8484
extern unsigned get_434_reg(unsigned reg_offs);
8585
extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
8686
extern unsigned char get_latch_u5(void);
87+
extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
88+
extern void rb532_gpio_set_istat(int bit, unsigned gpio);
8789

8890
#endif /* _RC32434_GPIO_H_ */

‎arch/mips/include/asm/mach-rc32434/rb.h

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -40,12 +40,14 @@
4040
#define BTCS 0x010040
4141
#define BTCOMPARE 0x010044
4242
#define GPIOBASE 0x050000
43-
#define GPIOCFG 0x050004
44-
#define GPIOD 0x050008
45-
#define GPIOILEVEL 0x05000C
46-
#define GPIOISTAT 0x050010
47-
#define GPIONMIEN 0x050014
48-
#define IMASK6 0x038038
43+
/* Offsets relative to GPIOBASE */
44+
#define GPIOFUNC 0x00
45+
#define GPIOCFG 0x04
46+
#define GPIOD 0x08
47+
#define GPIOILEVEL 0x0C
48+
#define GPIOISTAT 0x10
49+
#define GPIONMIEN 0x14
50+
#define IMASK6 0x38
4951
#define LO_WPX (1 << 0)
5052
#define LO_ALE (1 << 1)
5153
#define LO_CLE (1 << 2)

‎arch/mips/include/asm/time.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ static inline int mips_clockevent_init(void)
6363
/*
6464
* Initialize the count register as a clocksource
6565
*/
66-
#ifdef CONFIG_CEVT_R4K
66+
#ifdef CONFIG_CSRC_R4K
6767
extern int init_mips_clocksource(void);
6868
#else
6969
static inline int init_mips_clocksource(void)

‎arch/mips/kernel/csrc-r4k.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ int __init init_mips_clocksource(void)
2727
if (!cpu_has_counter || !mips_hpt_frequency)
2828
return -ENXIO;
2929

30-
/* Calclate a somewhat reasonable rating value */
30+
/* Calculate a somewhat reasonable rating value */
3131
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
3232

3333
clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);

‎arch/mips/mm/sc-ip22.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,7 @@ static inline int __init indy_sc_probe(void)
161161

162162
/* XXX Check with wje if the Indy caches can differenciate between
163163
writeback + invalidate and just invalidate. */
164-
struct bcache_ops indy_sc_ops = {
164+
static struct bcache_ops indy_sc_ops = {
165165
.bc_enable = indy_sc_enable,
166166
.bc_disable = indy_sc_disable,
167167
.bc_wback_inv = indy_sc_wback_invalidate,

‎arch/mips/mti-malta/malta-amon.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22,9 +22,9 @@
2222
#include <linux/init.h>
2323
#include <linux/smp.h>
2424

25-
#include <asm-mips/addrspace.h>
26-
#include <asm-mips/mips-boards/launch.h>
27-
#include <asm-mips/mipsmtregs.h>
25+
#include <asm/addrspace.h>
26+
#include <asm/mips-boards/launch.h>
27+
#include <asm/mipsmtregs.h>
2828

2929
int amon_cpu_avail(int cpu)
3030
{

‎arch/mips/rb532/devices.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = {
118118
/* Resources and device for NAND */
119119
static int rb532_dev_ready(struct mtd_info *mtd)
120120
{
121-
return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
121+
return gpio_get_value(GPIO_RDY);
122122
}
123123

124124
static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)

‎arch/mips/rb532/gpio.c

Lines changed: 73 additions & 120 deletions
Original file line numberDiff line numberDiff line change
@@ -39,10 +39,6 @@
3939
struct rb532_gpio_chip {
4040
struct gpio_chip chip;
4141
void __iomem *regbase;
42-
void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value);
43-
int (*get_int_level)(struct gpio_chip *chip, unsigned offset);
44-
void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value);
45-
int (*get_int_status)(struct gpio_chip *chip, unsigned offset);
4642
};
4743

4844
struct mpmc_device dev3;
@@ -111,15 +107,47 @@ unsigned char get_latch_u5(void)
111107
}
112108
EXPORT_SYMBOL(get_latch_u5);
113109

110+
/* rb532_set_bit - sanely set a bit
111+
*
112+
* bitval: new value for the bit
113+
* offset: bit index in the 4 byte address range
114+
* ioaddr: 4 byte aligned address being altered
115+
*/
116+
static inline void rb532_set_bit(unsigned bitval,
117+
unsigned offset, void __iomem *ioaddr)
118+
{
119+
unsigned long flags;
120+
u32 val;
121+
122+
bitval = !!bitval; /* map parameter to {0,1} */
123+
124+
local_irq_save(flags);
125+
126+
val = readl(ioaddr);
127+
val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */
128+
val |= ( bitval << offset ); /* set bit if bitval == 1 */
129+
writel(val, ioaddr);
130+
131+
local_irq_restore(flags);
132+
}
133+
134+
/* rb532_get_bit - read a bit
135+
*
136+
* returns the boolean state of the bit, which may be > 1
137+
*/
138+
static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
139+
{
140+
return (readl(ioaddr) & (1 << offset));
141+
}
142+
114143
/*
115144
* Return GPIO level */
116145
static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
117146
{
118-
u32 mask = 1 << offset;
119147
struct rb532_gpio_chip *gpch;
120148

121149
gpch = container_of(chip, struct rb532_gpio_chip, chip);
122-
return readl(gpch->regbase + GPIOD) & mask;
150+
return rb532_get_bit(offset, gpch->regbase + GPIOD);
123151
}
124152

125153
/*
@@ -128,45 +156,25 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
128156
static void rb532_gpio_set(struct gpio_chip *chip,
129157
unsigned offset, int value)
130158
{
131-
unsigned long flags;
132-
u32 mask = 1 << offset;
133-
u32 tmp;
134159
struct rb532_gpio_chip *gpch;
135-
void __iomem *gpvr;
136160

137161
gpch = container_of(chip, struct rb532_gpio_chip, chip);
138-
gpvr = gpch->regbase + GPIOD;
139-
140-
local_irq_save(flags);
141-
tmp = readl(gpvr);
142-
if (value)
143-
tmp |= mask;
144-
else
145-
tmp &= ~mask;
146-
writel(tmp, gpvr);
147-
local_irq_restore(flags);
162+
rb532_set_bit(value, offset, gpch->regbase + GPIOD);
148163
}
149164

150165
/*
151166
* Set GPIO direction to input
152167
*/
153168
static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
154169
{
155-
unsigned long flags;
156-
u32 mask = 1 << offset;
157-
u32 value;
158170
struct rb532_gpio_chip *gpch;
159-
void __iomem *gpdr;
160171

161172
gpch = container_of(chip, struct rb532_gpio_chip, chip);
162-
gpdr = gpch->regbase + GPIOCFG;
163173

164-
local_irq_save(flags);
165-
value = readl(gpdr);
166-
value &= ~mask;
167-
writel(value, gpdr);
168-
local_irq_restore(flags);
174+
if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
175+
return 1; /* alternate function, GPIOCFG is ignored */
169176

177+
rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
170178
return 0;
171179
}
172180

@@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
176184
static int rb532_gpio_direction_output(struct gpio_chip *chip,
177185
unsigned offset, int value)
178186
{
179-
unsigned long flags;
180-
u32 mask = 1 << offset;
181-
u32 tmp;
182187
struct rb532_gpio_chip *gpch;
183-
void __iomem *gpdr;
184188

185189
gpch = container_of(chip, struct rb532_gpio_chip, chip);
186-
writel(mask, gpch->regbase + GPIOD);
187-
gpdr = gpch->regbase + GPIOCFG;
188190

189-
local_irq_save(flags);
190-
tmp = readl(gpdr);
191-
tmp |= mask;
192-
writel(tmp, gpdr);
193-
local_irq_restore(flags);
191+
if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
192+
return 1; /* alternate function, GPIOCFG is ignored */
194193

194+
/* set the initial output value */
195+
rb532_set_bit(value, offset, gpch->regbase + GPIOD);
196+
197+
rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
195198
return 0;
196199
}
197200

198-
/*
199-
* Set the GPIO interrupt level
200-
*/
201-
static void rb532_gpio_set_int_level(struct gpio_chip *chip,
202-
unsigned offset, int value)
203-
{
204-
unsigned long flags;
205-
u32 mask = 1 << offset;
206-
u32 tmp;
207-
struct rb532_gpio_chip *gpch;
208-
void __iomem *gpil;
209-
210-
gpch = container_of(chip, struct rb532_gpio_chip, chip);
211-
gpil = gpch->regbase + GPIOILEVEL;
212-
213-
local_irq_save(flags);
214-
tmp = readl(gpil);
215-
if (value)
216-
tmp |= mask;
217-
else
218-
tmp &= ~mask;
219-
writel(tmp, gpil);
220-
local_irq_restore(flags);
221-
}
201+
static struct rb532_gpio_chip rb532_gpio_chip[] = {
202+
[0] = {
203+
.chip = {
204+
.label = "gpio0",
205+
.direction_input = rb532_gpio_direction_input,
206+
.direction_output = rb532_gpio_direction_output,
207+
.get = rb532_gpio_get,
208+
.set = rb532_gpio_set,
209+
.base = 0,
210+
.ngpio = 32,
211+
},
212+
},
213+
};
222214

223215
/*
224-
* Get the GPIO interrupt level
216+
* Set GPIO interrupt level
225217
*/
226-
static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset)
218+
void rb532_gpio_set_ilevel(int bit, unsigned gpio)
227219
{
228-
u32 mask = 1 << offset;
229-
struct rb532_gpio_chip *gpch;
230-
231-
gpch = container_of(chip, struct rb532_gpio_chip, chip);
232-
return readl(gpch->regbase + GPIOILEVEL) & mask;
220+
rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
233221
}
222+
EXPORT_SYMBOL(rb532_gpio_set_ilevel);
234223

235224
/*
236-
* Set the GPIO interrupt status
225+
* Set GPIO interrupt status
237226
*/
238-
static void rb532_gpio_set_int_status(struct gpio_chip *chip,
239-
unsigned offset, int value)
227+
void rb532_gpio_set_istat(int bit, unsigned gpio)
240228
{
241-
unsigned long flags;
242-
u32 mask = 1 << offset;
243-
u32 tmp;
244-
struct rb532_gpio_chip *gpch;
245-
void __iomem *gpis;
246-
247-
gpch = container_of(chip, struct rb532_gpio_chip, chip);
248-
gpis = gpch->regbase + GPIOISTAT;
249-
250-
local_irq_save(flags);
251-
tmp = readl(gpis);
252-
if (value)
253-
tmp |= mask;
254-
else
255-
tmp &= ~mask;
256-
writel(tmp, gpis);
257-
local_irq_restore(flags);
229+
rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
258230
}
231+
EXPORT_SYMBOL(rb532_gpio_set_istat);
259232

260233
/*
261-
* Get the GPIO interrupt status
234+
* Configure GPIO alternate function
262235
*/
263-
static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset)
236+
static void rb532_gpio_set_func(int bit, unsigned gpio)
264237
{
265-
u32 mask = 1 << offset;
266-
struct rb532_gpio_chip *gpch;
267-
268-
gpch = container_of(chip, struct rb532_gpio_chip, chip);
269-
return readl(gpch->regbase + GPIOISTAT) & mask;
238+
rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
270239
}
271240

272-
static struct rb532_gpio_chip rb532_gpio_chip[] = {
273-
[0] = {
274-
.chip = {
275-
.label = "gpio0",
276-
.direction_input = rb532_gpio_direction_input,
277-
.direction_output = rb532_gpio_direction_output,
278-
.get = rb532_gpio_get,
279-
.set = rb532_gpio_set,
280-
.base = 0,
281-
.ngpio = 32,
282-
},
283-
.get_int_level = rb532_gpio_get_int_level,
284-
.set_int_level = rb532_gpio_set_int_level,
285-
.get_int_status = rb532_gpio_get_int_status,
286-
.set_int_status = rb532_gpio_set_int_status,
287-
},
288-
};
289-
290241
int __init rb532_gpio_init(void)
291242
{
292243
struct resource *r;
@@ -310,9 +261,11 @@ int __init rb532_gpio_init(void)
310261
return -ENXIO;
311262
}
312263

313-
/* Set the interrupt status and level for the CF pin */
314-
rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1);
315-
rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0);
264+
/* configure CF_GPIO_NUM as CFRDY IRQ source */
265+
rb532_gpio_set_func(0, CF_GPIO_NUM);
266+
rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
267+
rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
268+
rb532_gpio_set_istat(0, CF_GPIO_NUM);
316269

317270
return 0;
318271
}

0 commit comments

Comments
 (0)