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int pci_msi_setup_msi_irqs (struct pci_dev * dev , int nvec , int type );
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void pci_msi_teardown_msi_irqs (struct pci_dev * dev );
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- #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
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- int pci_msi_legacy_setup_msi_irqs (struct pci_dev * dev , int nvec , int type );
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- void pci_msi_legacy_teardown_msi_irqs (struct pci_dev * dev );
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- #else
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- static inline int pci_msi_legacy_setup_msi_irqs (struct pci_dev * dev , int nvec , int type )
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+ /* Mask/unmask helpers */
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+ void pci_msi_update_mask (struct msi_desc * desc , u32 clear , u32 set );
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+
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+ static inline void pci_msi_mask (struct msi_desc * desc , u32 mask )
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{
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- WARN_ON_ONCE (1 );
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- return - ENODEV ;
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+ pci_msi_update_mask (desc , 0 , mask );
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}
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- static inline void pci_msi_legacy_teardown_msi_irqs (struct pci_dev * dev )
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+ static inline void pci_msi_unmask (struct msi_desc * desc , u32 mask )
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{
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- WARN_ON_ONCE (1 );
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+ pci_msi_update_mask (desc , mask , 0 );
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+ }
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+
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+ static inline void __iomem * pci_msix_desc_addr (struct msi_desc * desc )
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+ {
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+ return desc -> pci .mask_base + desc -> msi_index * PCI_MSIX_ENTRY_SIZE ;
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+ }
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+
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+ /*
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+ * This internal function does not flush PCI writes to the device. All
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+ * users must ensure that they read from the device before either assuming
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+ * that the device state is up to date, or returning out of this file.
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+ * It does not affect the msi_desc::msix_ctrl cache either. Use with care!
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+ */
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+ static inline void pci_msix_write_vector_ctrl (struct msi_desc * desc , u32 ctrl )
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+ {
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+ void __iomem * desc_addr = pci_msix_desc_addr (desc );
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+
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+ if (desc -> pci .msi_attrib .can_mask )
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+ writel (ctrl , desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL );
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+ }
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+
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+ static inline void pci_msix_mask (struct msi_desc * desc )
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+ {
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+ desc -> pci .msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT ;
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+ pci_msix_write_vector_ctrl (desc , desc -> pci .msix_ctrl );
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+ /* Flush write to device */
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+ readl (desc -> pci .mask_base );
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+ }
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+
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+ static inline void pci_msix_unmask (struct msi_desc * desc )
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+ {
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+ desc -> pci .msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT ;
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+ pci_msix_write_vector_ctrl (desc , desc -> pci .msix_ctrl );
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+ }
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+
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+ static inline void __pci_msi_mask_desc (struct msi_desc * desc , u32 mask )
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+ {
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+ if (desc -> pci .msi_attrib .is_msix )
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+ pci_msix_mask (desc );
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+ else
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+ pci_msi_mask (desc , mask );
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+ }
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+
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+ static inline void __pci_msi_unmask_desc (struct msi_desc * desc , u32 mask )
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+ {
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+ if (desc -> pci .msi_attrib .is_msix )
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+ pci_msix_unmask (desc );
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+ else
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+ pci_msi_unmask (desc , mask );
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}
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- #endif
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/*
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* PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
@@ -37,3 +83,20 @@ static inline __attribute_const__ u32 msi_multi_mask(struct msi_desc *desc)
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return 0xffffffff ;
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return (1 << (1 << desc -> pci .msi_attrib .multi_cap )) - 1 ;
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}
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+
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+ /* Legacy (!IRQDOMAIN) fallbacks */
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+ #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
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+ int pci_msi_legacy_setup_msi_irqs (struct pci_dev * dev , int nvec , int type );
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+ void pci_msi_legacy_teardown_msi_irqs (struct pci_dev * dev );
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+ #else
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+ static inline int pci_msi_legacy_setup_msi_irqs (struct pci_dev * dev , int nvec , int type )
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+ {
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+ WARN_ON_ONCE (1 );
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+ return - ENODEV ;
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+ }
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+
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+ static inline void pci_msi_legacy_teardown_msi_irqs (struct pci_dev * dev )
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+ {
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+ WARN_ON_ONCE (1 );
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+ }
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+ #endif
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