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ARM: dts: exynos: Add USB to Exynos5410
Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to exynos54xx.dtsi common for entire family. For Exynos542x/5800 this should not have functional impact but for Exynos5410 this effectively adds USB support. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Tested-by: Javier Martinez Canillas <[email protected]>
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-94
lines changed

3 files changed

+157
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‎arch/arm/boot/dts/exynos5410.dtsi

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -188,4 +188,43 @@
188188
3 0 0x07000000 0x20000>;
189189
};
190190

191+
&usbdrd3_0 {
192+
clocks = <&clock CLK_USBD300>;
193+
clock-names = "usbdrd30";
194+
};
195+
196+
&usbdrd_phy0 {
197+
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
198+
clock-names = "phy", "ref";
199+
samsung,pmu-syscon = <&pmu_system_controller>;
200+
};
201+
202+
&usbdrd3_1 {
203+
clocks = <&clock CLK_USBD301>;
204+
clock-names = "usbdrd30";
205+
};
206+
207+
&usbdrd_phy1 {
208+
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
209+
clock-names = "phy", "ref";
210+
samsung,pmu-syscon = <&pmu_system_controller>;
211+
};
212+
213+
&usbhost1 {
214+
clocks = <&clock CLK_USBH20>;
215+
clock-names = "usbhost";
216+
};
217+
218+
&usbhost2 {
219+
clocks = <&clock CLK_USBH20>;
220+
clock-names = "usbhost";
221+
};
222+
223+
&usb2_phy {
224+
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
225+
clock-names = "phy", "ref";
226+
samsung,sysreg-phandle = <&sysreg_system_controller>;
227+
samsung,pmureg-phandle = <&pmu_system_controller>;
228+
};
229+
191230
#include "exynos5410-pinctrl.dtsi"

‎arch/arm/boot/dts/exynos5420.dtsi

Lines changed: 39 additions & 94 deletions
Original file line numberDiff line numberDiff line change
@@ -41,8 +41,6 @@
4141
spi0 = &spi_0;
4242
spi1 = &spi_1;
4343
spi2 = &spi_2;
44-
usbdrdphy0 = &usbdrd_phy0;
45-
usbdrdphy1 = &usbdrd_phy1;
4644
};
4745

4846
/*
@@ -806,98 +804,6 @@
806804
clock-names = "secss";
807805
};
808806

809-
usbdrd3_0: usb3-0 {
810-
compatible = "samsung,exynos5250-dwusb3";
811-
clocks = <&clock CLK_USBD300>;
812-
clock-names = "usbdrd30";
813-
#address-cells = <1>;
814-
#size-cells = <1>;
815-
ranges;
816-
817-
usbdrd_dwc3_0: dwc3@12000000 {
818-
compatible = "snps,dwc3";
819-
reg = <0x12000000 0x10000>;
820-
interrupts = <0 72 0>;
821-
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
822-
phy-names = "usb2-phy", "usb3-phy";
823-
};
824-
};
825-
826-
usbdrd_phy0: phy@12100000 {
827-
compatible = "samsung,exynos5420-usbdrd-phy";
828-
reg = <0x12100000 0x100>;
829-
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
830-
clock-names = "phy", "ref";
831-
samsung,pmu-syscon = <&pmu_system_controller>;
832-
#phy-cells = <1>;
833-
};
834-
835-
usbdrd3_1: usb3-1 {
836-
compatible = "samsung,exynos5250-dwusb3";
837-
clocks = <&clock CLK_USBD301>;
838-
clock-names = "usbdrd30";
839-
#address-cells = <1>;
840-
#size-cells = <1>;
841-
ranges;
842-
843-
usbdrd_dwc3_1: dwc3@12400000 {
844-
compatible = "snps,dwc3";
845-
reg = <0x12400000 0x10000>;
846-
interrupts = <0 73 0>;
847-
phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
848-
phy-names = "usb2-phy", "usb3-phy";
849-
};
850-
};
851-
852-
usbdrd_phy1: phy@12500000 {
853-
compatible = "samsung,exynos5420-usbdrd-phy";
854-
reg = <0x12500000 0x100>;
855-
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
856-
clock-names = "phy", "ref";
857-
samsung,pmu-syscon = <&pmu_system_controller>;
858-
#phy-cells = <1>;
859-
};
860-
861-
usbhost2: usb@12110000 {
862-
compatible = "samsung,exynos4210-ehci";
863-
reg = <0x12110000 0x100>;
864-
interrupts = <0 71 0>;
865-
866-
clocks = <&clock CLK_USBH20>;
867-
clock-names = "usbhost";
868-
#address-cells = <1>;
869-
#size-cells = <0>;
870-
port@0 {
871-
reg = <0>;
872-
phys = <&usb2_phy 1>;
873-
};
874-
};
875-
876-
usbhost1: usb@12120000 {
877-
compatible = "samsung,exynos4210-ohci";
878-
reg = <0x12120000 0x100>;
879-
interrupts = <0 71 0>;
880-
881-
clocks = <&clock CLK_USBH20>;
882-
clock-names = "usbhost";
883-
#address-cells = <1>;
884-
#size-cells = <0>;
885-
port@0 {
886-
reg = <0>;
887-
phys = <&usb2_phy 1>;
888-
};
889-
};
890-
891-
usb2_phy: phy@12130000 {
892-
compatible = "samsung,exynos5250-usb2-phy";
893-
reg = <0x12130000 0x100>;
894-
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
895-
clock-names = "phy", "ref";
896-
#phy-cells = <1>;
897-
samsung,sysreg-phandle = <&sysreg_system_controller>;
898-
samsung,pmureg-phandle = <&pmu_system_controller>;
899-
};
900-
901807
sysmmu_g2dr: sysmmu@0x10A60000 {
902808
compatible = "samsung,exynos-sysmmu";
903809
reg = <0x10A60000 0x1000>;
@@ -1560,4 +1466,43 @@
15601466
clock-names = "uart", "clk_uart_baud0";
15611467
};
15621468

1469+
&usbdrd3_0 {
1470+
clocks = <&clock CLK_USBD300>;
1471+
clock-names = "usbdrd30";
1472+
};
1473+
1474+
&usbdrd_phy0 {
1475+
clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
1476+
clock-names = "phy", "ref";
1477+
samsung,pmu-syscon = <&pmu_system_controller>;
1478+
};
1479+
1480+
&usbdrd3_1 {
1481+
clocks = <&clock CLK_USBD301>;
1482+
clock-names = "usbdrd30";
1483+
};
1484+
1485+
&usbdrd_phy1 {
1486+
clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
1487+
clock-names = "phy", "ref";
1488+
samsung,pmu-syscon = <&pmu_system_controller>;
1489+
};
1490+
1491+
&usbhost1 {
1492+
clocks = <&clock CLK_USBH20>;
1493+
clock-names = "usbhost";
1494+
};
1495+
1496+
&usbhost2 {
1497+
clocks = <&clock CLK_USBH20>;
1498+
clock-names = "usbhost";
1499+
};
1500+
1501+
&usb2_phy {
1502+
clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
1503+
clock-names = "phy", "ref";
1504+
samsung,sysreg-phandle = <&sysreg_system_controller>;
1505+
samsung,pmureg-phandle = <&pmu_system_controller>;
1506+
};
1507+
15631508
#include "exynos5420-pinctrl.dtsi"

‎arch/arm/boot/dts/exynos54xx.dtsi

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,11 @@
2020
/ {
2121
compatible = "samsung,exynos5";
2222

23+
aliases {
24+
usbdrdphy0 = &usbdrd_phy0;
25+
usbdrdphy1 = &usbdrd_phy1;
26+
};
27+
2328
soc: soc {
2429
sysram@02020000 {
2530
compatible = "mmio-sram";
@@ -64,5 +69,79 @@
6469
<11 &gic 0 131 0>;
6570
};
6671
};
72+
73+
usbdrd3_0: usb3-0 {
74+
compatible = "samsung,exynos5250-dwusb3";
75+
#address-cells = <1>;
76+
#size-cells = <1>;
77+
ranges;
78+
79+
usbdrd_dwc3_0: dwc3@12000000 {
80+
compatible = "snps,dwc3";
81+
reg = <0x12000000 0x10000>;
82+
interrupts = <0 72 0>;
83+
phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
84+
phy-names = "usb2-phy", "usb3-phy";
85+
};
86+
};
87+
88+
usbdrd_phy0: phy@12100000 {
89+
compatible = "samsung,exynos5420-usbdrd-phy";
90+
reg = <0x12100000 0x100>;
91+
#phy-cells = <1>;
92+
};
93+
94+
usbdrd3_1: usb3-1 {
95+
compatible = "samsung,exynos5250-dwusb3";
96+
#address-cells = <1>;
97+
#size-cells = <1>;
98+
ranges;
99+
100+
usbdrd_dwc3_1: dwc3@12400000 {
101+
compatible = "snps,dwc3";
102+
reg = <0x12400000 0x10000>;
103+
interrupts = <0 73 0>;
104+
phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
105+
phy-names = "usb2-phy", "usb3-phy";
106+
};
107+
};
108+
109+
usbdrd_phy1: phy@12500000 {
110+
compatible = "samsung,exynos5420-usbdrd-phy";
111+
reg = <0x12500000 0x100>;
112+
#phy-cells = <1>;
113+
};
114+
115+
usbhost2: usb@12110000 {
116+
compatible = "samsung,exynos4210-ehci";
117+
reg = <0x12110000 0x100>;
118+
interrupts = <0 71 0>;
119+
120+
#address-cells = <1>;
121+
#size-cells = <0>;
122+
port@0 {
123+
reg = <0>;
124+
phys = <&usb2_phy 1>;
125+
};
126+
};
127+
128+
usbhost1: usb@12120000 {
129+
compatible = "samsung,exynos4210-ohci";
130+
reg = <0x12120000 0x100>;
131+
interrupts = <0 71 0>;
132+
133+
#address-cells = <1>;
134+
#size-cells = <0>;
135+
port@0 {
136+
reg = <0>;
137+
phys = <&usb2_phy 1>;
138+
};
139+
};
140+
141+
usb2_phy: phy@12130000 {
142+
compatible = "samsung,exynos5250-usb2-phy";
143+
reg = <0x12130000 0x100>;
144+
#phy-cells = <1>;
145+
};
67146
};
68147
};

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