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andy-shevdavem330
andy-shev
authored and
davem330
committed
stmmac: intel: Fix indentation to put on one line affected code
There is no competition to get more LOCs into the kernel, and driver can look better and have improved readability without those additional line breaks. While at it, shorten info structures that they are all PCI, at the end it's a PCI driver for Intel hardware. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

Lines changed: 32 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -83,13 +83,9 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
8383
serdes_phy_addr = intel_priv->mdio_adhoc_addr;
8484

8585
/* assert clk_req */
86-
data = mdiobus_read(priv->mii, serdes_phy_addr,
87-
SERDES_GCR0);
88-
86+
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
8987
data |= SERDES_PLL_CLK;
90-
91-
mdiobus_write(priv->mii, serdes_phy_addr,
92-
SERDES_GCR0, data);
88+
mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
9389

9490
/* check for clk_ack assertion */
9591
data = serdes_status_poll(priv, serdes_phy_addr,
@@ -103,13 +99,9 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
10399
}
104100

105101
/* assert lane reset */
106-
data = mdiobus_read(priv->mii, serdes_phy_addr,
107-
SERDES_GCR0);
108-
102+
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
109103
data |= SERDES_RST;
110-
111-
mdiobus_write(priv->mii, serdes_phy_addr,
112-
SERDES_GCR0, data);
104+
mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
113105

114106
/* check for assert lane reset reflection */
115107
data = serdes_status_poll(priv, serdes_phy_addr,
@@ -123,14 +115,12 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
123115
}
124116

125117
/* move power state to P0 */
126-
data = mdiobus_read(priv->mii, serdes_phy_addr,
127-
SERDES_GCR0);
118+
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
128119

129120
data &= ~SERDES_PWR_ST_MASK;
130121
data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
131122

132-
mdiobus_write(priv->mii, serdes_phy_addr,
133-
SERDES_GCR0, data);
123+
mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
134124

135125
/* Check for P0 state */
136126
data = serdes_status_poll(priv, serdes_phy_addr,
@@ -159,14 +149,12 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
159149
serdes_phy_addr = intel_priv->mdio_adhoc_addr;
160150

161151
/* move power state to P3 */
162-
data = mdiobus_read(priv->mii, serdes_phy_addr,
163-
SERDES_GCR0);
152+
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
164153

165154
data &= ~SERDES_PWR_ST_MASK;
166155
data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
167156

168-
mdiobus_write(priv->mii, serdes_phy_addr,
169-
SERDES_GCR0, data);
157+
mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
170158

171159
/* Check for P3 state */
172160
data = serdes_status_poll(priv, serdes_phy_addr,
@@ -180,13 +168,9 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
180168
}
181169

182170
/* de-assert clk_req */
183-
data = mdiobus_read(priv->mii, serdes_phy_addr,
184-
SERDES_GCR0);
185-
171+
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
186172
data &= ~SERDES_PLL_CLK;
187-
188-
mdiobus_write(priv->mii, serdes_phy_addr,
189-
SERDES_GCR0, data);
173+
mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
190174

191175
/* check for clk_ack de-assert */
192176
data = serdes_status_poll(priv, serdes_phy_addr,
@@ -200,13 +184,9 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
200184
}
201185

202186
/* de-assert lane reset */
203-
data = mdiobus_read(priv->mii, serdes_phy_addr,
204-
SERDES_GCR0);
205-
187+
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
206188
data &= ~SERDES_RST;
207-
208-
mdiobus_write(priv->mii, serdes_phy_addr,
209-
SERDES_GCR0, data);
189+
mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
210190

211191
/* check for de-assert lane reset reflection */
212192
data = serdes_status_poll(priv, serdes_phy_addr,
@@ -367,7 +347,7 @@ static int ehl_sgmii_data(struct pci_dev *pdev,
367347
return ehl_common_data(pdev, plat);
368348
}
369349

370-
static struct stmmac_pci_info ehl_sgmii1g_pci_info = {
350+
static struct stmmac_pci_info ehl_sgmii1g_info = {
371351
.setup = ehl_sgmii_data,
372352
};
373353

@@ -381,7 +361,7 @@ static int ehl_rgmii_data(struct pci_dev *pdev,
381361
return ehl_common_data(pdev, plat);
382362
}
383363

384-
static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
364+
static struct stmmac_pci_info ehl_rgmii1g_info = {
385365
.setup = ehl_rgmii_data,
386366
};
387367

@@ -400,7 +380,7 @@ static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
400380
return ehl_pse0_common_data(pdev, plat);
401381
}
402382

403-
static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = {
383+
static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
404384
.setup = ehl_pse0_rgmii1g_data,
405385
};
406386

@@ -413,7 +393,7 @@ static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
413393
return ehl_pse0_common_data(pdev, plat);
414394
}
415395

416-
static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = {
396+
static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
417397
.setup = ehl_pse0_sgmii1g_data,
418398
};
419399

@@ -432,7 +412,7 @@ static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
432412
return ehl_pse1_common_data(pdev, plat);
433413
}
434414

435-
static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = {
415+
static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
436416
.setup = ehl_pse1_rgmii1g_data,
437417
};
438418

@@ -445,7 +425,7 @@ static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
445425
return ehl_pse1_common_data(pdev, plat);
446426
}
447427

448-
static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = {
428+
static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
449429
.setup = ehl_pse1_sgmii1g_data,
450430
};
451431

@@ -470,7 +450,7 @@ static int tgl_sgmii_data(struct pci_dev *pdev,
470450
return tgl_common_data(pdev, plat);
471451
}
472452

473-
static struct stmmac_pci_info tgl_sgmii1g_pci_info = {
453+
static struct stmmac_pci_info tgl_sgmii1g_info = {
474454
.setup = tgl_sgmii_data,
475455
};
476456

@@ -573,7 +553,7 @@ static int quark_default_data(struct pci_dev *pdev,
573553
return 0;
574554
}
575555

576-
static const struct stmmac_pci_info quark_pci_info = {
556+
static const struct stmmac_pci_info quark_info = {
577557
.setup = quark_default_data,
578558
};
579559

@@ -598,8 +578,7 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
598578
struct stmmac_resources res;
599579
int ret;
600580

601-
intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv),
602-
GFP_KERNEL);
581+
intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
603582
if (!intel_priv)
604583
return -ENOMEM;
605584

@@ -736,26 +715,19 @@ static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
736715
#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
737716

738717
static const struct pci_device_id intel_eth_pci_id_table[] = {
739-
{ PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) },
740-
{ PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) },
741-
{ PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) },
742-
{ PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_pci_info) },
743-
{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID,
744-
&ehl_pse0_rgmii1g_pci_info) },
745-
{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID,
746-
&ehl_pse0_sgmii1g_pci_info) },
747-
{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID,
748-
&ehl_pse0_sgmii1g_pci_info) },
749-
{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID,
750-
&ehl_pse1_rgmii1g_pci_info) },
751-
{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID,
752-
&ehl_pse1_sgmii1g_pci_info) },
753-
{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID,
754-
&ehl_pse1_sgmii1g_pci_info) },
755-
{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) },
718+
{ PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_info) },
719+
{ PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_info) },
720+
{ PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_info) },
721+
{ PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_info) },
722+
{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, &ehl_pse0_rgmii1g_info) },
723+
{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, &ehl_pse0_sgmii1g_info) },
724+
{ PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, &ehl_pse0_sgmii1g_info) },
725+
{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, &ehl_pse1_rgmii1g_info) },
726+
{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, &ehl_pse1_sgmii1g_info) },
727+
{ PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, &ehl_pse1_sgmii1g_info) },
728+
{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_info) },
756729
{}
757730
};
758-
759731
MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
760732

761733
static struct pci_driver intel_eth_pci_driver = {

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