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elkablodavem330
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net: phy: marvell10g: support other MACTYPEs
Currently the only "changing" MACTYPE we support is when the PHY changes between 10gbase-r / 5gbase-r / 2500base-x / sgmii Add support for usxgmii xaui / 5gbase-r / 2500base-x / sgmii rxaui / 5gbase-r / 2500base-x / sgmii and also 5gbase-r / 2500base-x / sgmii for 88E2110. Signed-off-by: Marek Behún <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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drivers/net/phy/marvell10g.c

Lines changed: 54 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -512,10 +512,18 @@ static int mv2110_init_interface(struct phy_device *phydev, int mactype)
512512

513513
priv->rate_match = false;
514514

515-
if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH) {
515+
if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
516516
priv->rate_match = true;
517+
518+
if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_USXGMII)
519+
priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
520+
else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
517521
priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
518-
}
522+
else if (mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER ||
523+
mactype == MV_PMA_21X0_PORT_CTRL_MACTYPE_5GBASER_NO_SGMII_AN)
524+
priv->const_interface = PHY_INTERFACE_MODE_NA;
525+
else
526+
return -EINVAL;
519527

520528
return 0;
521529
}
@@ -531,12 +539,20 @@ static int mv3310_init_interface(struct phy_device *phydev, int mactype)
531539
mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
532540
priv->rate_match = true;
533541

534-
if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH)
542+
if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII)
543+
priv->const_interface = PHY_INTERFACE_MODE_USXGMII;
544+
else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH ||
545+
mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN ||
546+
mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER)
535547
priv->const_interface = PHY_INTERFACE_MODE_10GBASER;
536-
else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH)
548+
else if (mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH ||
549+
mactype == MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI)
537550
priv->const_interface = PHY_INTERFACE_MODE_RXAUI;
538-
else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH)
551+
else if (mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH ||
552+
mactype == MV_V2_3310_PORT_CTRL_MACTYPE_XAUI)
539553
priv->const_interface = PHY_INTERFACE_MODE_XAUI;
554+
else
555+
return -EINVAL;
540556

541557
return 0;
542558
}
@@ -563,8 +579,10 @@ static int mv3310_config_init(struct phy_device *phydev)
563579
return mactype;
564580

565581
err = chip->init_interface(phydev, mactype);
566-
if (err)
582+
if (err) {
583+
phydev_err(phydev, "MACTYPE configuration invalid\n");
567584
return err;
585+
}
568586

569587
/* Enable EDPD mode - saving 600mW */
570588
return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
@@ -674,44 +692,44 @@ static void mv3310_update_interface(struct phy_device *phydev)
674692
{
675693
struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
676694

695+
if (!phydev->link)
696+
return;
697+
677698
/* In all of the "* with Rate Matching" modes the PHY interface is fixed
678699
* at 10Gb. The PHY adapts the rate to actual wire speed with help of
679700
* internal 16KB buffer.
701+
*
702+
* In USXGMII mode the PHY interface mode is also fixed.
680703
*/
681-
if (priv->rate_match) {
704+
if (priv->rate_match ||
705+
priv->const_interface == PHY_INTERFACE_MODE_USXGMII) {
682706
phydev->interface = priv->const_interface;
683707
return;
684708
}
685709

686-
if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
687-
phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
688-
phydev->interface == PHY_INTERFACE_MODE_5GBASER ||
689-
phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
690-
phydev->link) {
691-
/* The PHY automatically switches its serdes interface (and
692-
* active PHYXS instance) between Cisco SGMII, 10GBase-R and
693-
* 2500BaseX modes according to the speed. Florian suggests
694-
* setting phydev->interface to communicate this to the MAC.
695-
* Only do this if we are already in one of the above modes.
696-
*/
697-
switch (phydev->speed) {
698-
case SPEED_10000:
699-
phydev->interface = PHY_INTERFACE_MODE_10GBASER;
700-
break;
701-
case SPEED_5000:
702-
phydev->interface = PHY_INTERFACE_MODE_5GBASER;
703-
break;
704-
case SPEED_2500:
705-
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
706-
break;
707-
case SPEED_1000:
708-
case SPEED_100:
709-
case SPEED_10:
710-
phydev->interface = PHY_INTERFACE_MODE_SGMII;
711-
break;
712-
default:
713-
break;
714-
}
710+
/* The PHY automatically switches its serdes interface (and active PHYXS
711+
* instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R /
712+
* xaui / rxaui modes according to the speed.
713+
* Florian suggests setting phydev->interface to communicate this to the
714+
* MAC. Only do this if we are already in one of the above modes.
715+
*/
716+
switch (phydev->speed) {
717+
case SPEED_10000:
718+
phydev->interface = priv->const_interface;
719+
break;
720+
case SPEED_5000:
721+
phydev->interface = PHY_INTERFACE_MODE_5GBASER;
722+
break;
723+
case SPEED_2500:
724+
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
725+
break;
726+
case SPEED_1000:
727+
case SPEED_100:
728+
case SPEED_10:
729+
phydev->interface = PHY_INTERFACE_MODE_SGMII;
730+
break;
731+
default:
732+
break;
715733
}
716734
}
717735

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