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Merge tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull DeviceTree changes from Rob Herring: - DT unittests for I2C probing and overlays from Pantelis Antoniou - Remove DT unittest dependency on OF_DYNAMIC from Gaurav Minocha - Add Tegra compatible strings missing for newer parts from Paul Walmsley - Various vendor prefix additions * tag 'devicetree-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: of: Add vendor prefix for OmniVision Technologies of: Use ovti for Omnivision of: Add vendor prefix for Truly Semiconductors Limited of: Add vendor prefix for Himax Technologies Inc. of/fdt: fix sparse warning of: unitest: Add I2C overlay unit tests. Documentation: DT: document compatible string existence requirement Documentation: DT bindings: add nvidia, tegra132-denver compatible string Documentation: DT bindings: add more Tegra chip compatible strings of: EXPORT_SYMBOL_GPL of_property_read_u64_array of: Fix brace position for struct of_device_id definition of/unittest: Remove obsolete code dt-bindings: use isil prefix for Intersil in vendor-prefixes.txt Add AD Holdings Plc. to vendor-prefixes. dt-bindings: Add Silicon Mitus vendor prefix Removes OF_UNITTEST dependency on OF_DYNAMIC config symbol pinctrl: fix up device tree bindings DT: Vendors: Add Everspin doc: add bindings document for altera fpga manager drivers: of: Export of_reserved_mem_device_{init,release}
2 parents 42cf0f2 + 3c3c8e3 commit cdd3054

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‎Documentation/devicetree/bindings/arm/cpus.txt

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@@ -175,6 +175,7 @@ nodes to be present and contain the properties described below.
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"marvell,pj4a"
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"marvell,pj4b"
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"marvell,sheeva-v5"
178+
"nvidia,tegra132-denver"
178179
"qcom,krait"
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"qcom,scorpion"
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- enable-method

‎Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt

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@@ -1,7 +1,10 @@
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NVIDIA Tegra AHB
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33
Required properties:
4-
- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"
4+
- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5+
Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6+
'"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
7+
tegra132, or tegra210.
58
- reg : Should contain 1 register ranges(address and length)
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Example:

‎Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt

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@@ -6,7 +6,11 @@ modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
9-
- compatible : Should contain "nvidia,tegra<chip>-pmc".
9+
- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
10+
must contain "nvidia,tegra30-pmc". For Tegra114, must contain
11+
"nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
12+
Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
13+
above, where <chip> is tegra132.
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.

‎Documentation/devicetree/bindings/ata/tegra-sata.txt

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@@ -1,7 +1,9 @@
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Tegra124 SoC SATA AHCI controller
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Required properties :
4-
- compatible : "nvidia,tegra124-ahci".
4+
- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
5+
must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
6+
is tegra132.
57
- reg : Should contain 2 entries:
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- AHCI register set (SATA BAR5)
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- SATA register set

‎Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt

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@@ -0,0 +1,17 @@
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Altera SOCFPGA FPGA Manager
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3+
Required properties:
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- compatible : should contain "altr,socfpga-fpga-mgr"
5+
- reg : base address and size for memory mapped io.
6+
- The first index is for FPGA manager register access.
7+
- The second index is for writing FPGA configuration data.
8+
- interrupts : interrupt for the FPGA Manager device.
9+
10+
Example:
11+
12+
hps_0_fpgamgr: fpgamgr@0xff706000 {
13+
compatible = "altr,socfpga-fpga-mgr";
14+
reg = <0xFF706000 0x1000
15+
0xFFB90000 0x1000>;
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interrupts = <0 175 4>;
17+
};

‎Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt

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@@ -1,11 +1,11 @@
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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
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Required properties:
4-
- compatible : should be:
5-
"nvidia,tegra20-efuse"
6-
"nvidia,tegra30-efuse"
7-
"nvidia,tegra114-efuse"
8-
"nvidia,tegra124-efuse"
4+
- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
5+
must contain "nvidia,tegra30-efuse". For Tegra114, must contain
6+
"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
7+
Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
8+
<chip> is tegra132.
99
Details:
1010
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
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due to a hardware bug. Tegra20 also lacks certain information which is

‎Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

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@@ -197,7 +197,9 @@ of the following host1x client modules:
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- sor: serial output resource
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Required properties:
200-
- compatible: "nvidia,tegra124-sor"
200+
- compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
201+
must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
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is tegra132.
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.
@@ -222,7 +224,9 @@ of the following host1x client modules:
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- nvidia,dpaux: phandle to a DispayPort AUX interface
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- dpaux: DisplayPort AUX interface
225-
- compatible: "nvidia,tegra124-dpaux"
227+
- compatible: For Tegra124, must contain "nvidia,tegra124-dpaux". Otherwise,
228+
must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
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<chip> is tegra132.
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- reg: Physical base address and length of the controller's registers.
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- interrupts: The interrupt outputs from the controller.
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- clocks: Must contain an entry for each entry in clock-names.

‎Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt

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NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
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Required properties:
4-
- compatible : should be:
5-
"nvidia,tegra114-i2c"
6-
"nvidia,tegra30-i2c"
7-
"nvidia,tegra20-i2c"
8-
"nvidia,tegra20-i2c-dvc"
4+
- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or
5+
"nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c".
6+
For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be
7+
"nvidia,<chip>-i2c", plus at least one of the above, where <chip> is
8+
tegra124, tegra132, or tegra210.
99
Details of compatible are as follows:
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nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
1111
controller. This only support master mode of I2C communication. Register

‎Documentation/devicetree/bindings/media/atmel-isi.txt

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@@ -38,7 +38,7 @@ Example:
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i2c1: i2c@f0018000 {
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ov2640: camera@0x30 {
41-
compatible = "omnivision,ov2640";
41+
compatible = "ovti,ov2640";
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reg = <0x30>;
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port {

‎Documentation/devicetree/bindings/media/video-interfaces.txt

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@@ -162,7 +162,7 @@ pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
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i2c0: i2c@0xfff20000 {
163163
...
164164
ov772x_1: camera@0x21 {
165-
compatible = "omnivision,ov772x";
165+
compatible = "ovti,ov772x";
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reg = <0x21>;
167167
vddio-supply = <&regulator1>;
168168
vddcore-supply = <&regulator2>;

‎Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt

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NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 apbmisc block
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33
Required properties:
4-
- compatible : should be:
5-
"nvidia,tegra20-apbmisc"
6-
"nvidia,tegra30-apbmisc"
7-
"nvidia,tegra114-apbmisc"
8-
"nvidia,tegra124-apbmisc"
4+
- compatible : For Tegra20, must be "nvidia,tegra20-apbmisc". For Tegra30,
5+
must be "nvidia,tegra30-apbmisc". Otherwise, must contain
6+
"nvidia,<chip>-apbmisc", plus one of the above, where <chip> is tegra114,
7+
tegra124, tegra132.
98
- reg: Should contain 2 entries: the first entry gives the physical address
109
and length of the registers which contain revision and debug features.
1110
The second entry gives the physical address and length of the

‎Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt

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@@ -7,7 +7,11 @@ This file documents differences between the core properties described
77
by mmc.txt and the properties used by the sdhci-tegra driver.
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99
Required properties:
10-
- compatible : Should be "nvidia,<chip>-sdhci"
10+
- compatible : For Tegra20, must contain "nvidia,tegra20-sdhci".
11+
For Tegra30, must contain "nvidia,tegra30-sdhci". For Tegra114,
12+
must contain "nvidia,tegra114-sdhci". For Tegra124, must contain
13+
"nvidia,tegra124-sdhci". Otherwise, must contain "nvidia,<chip>-sdhci",
14+
plus one of the above, where <chip> is tegra132 or tegra210.
1115
- clocks : Must contain one entry, for the module clock.
1216
See ../clocks/clock-bindings.txt for details.
1317
- resets : Must contain an entry for each entry in reset-names.

‎Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

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11
NVIDIA Tegra PCIe controller
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33
Required properties:
4-
- compatible: Must be one of:
5-
- "nvidia,tegra20-pcie"
6-
- "nvidia,tegra30-pcie"
7-
- "nvidia,tegra124-pcie"
4+
- compatible: For Tegra20, must contain "nvidia,tegra20-pcie". For Tegra30,
5+
"nvidia,tegra30-pcie". For Tegra124, must contain "nvidia,tegra124-pcie".
6+
Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
7+
<chip> is tegra132 or tegra210.
88
- device_type: Must be "pci"
99
- reg: A list of physical base address and length for each set of controller
1010
registers. Must contain an entry for each entry in the reg-names property.

‎Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt

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@@ -6,7 +6,8 @@ nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
66
a baseline, and only documents the differences between the two bindings.
77

88
Required properties:
9-
- compatible: "nvidia,tegra124-pinmux"
9+
- compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
10+
Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
1011
- reg: Should contain a list of base address and size pairs for:
1112
-- first entry - the drive strength and pad control registers.
1213
-- second entry - the pinmux registers

‎Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt

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@@ -13,7 +13,9 @@ how to describe and reference PHYs in device trees.
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1414
Required properties:
1515
--------------------
16-
- compatible: should be "nvidia,tegra124-xusb-padctl"
16+
- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
17+
Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
18+
"nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
1719
- reg: Physical base address and length of the controller's registers.
1820
- resets: Must contain an entry for each entry in reset-names.
1921
See ../reset/reset.txt for details.

‎Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt

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11
Tegra SoC PWFM controller
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33
Required properties:
4-
- compatible: should be one of:
5-
- "nvidia,tegra20-pwm"
6-
- "nvidia,tegra30-pwm"
4+
- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30,
5+
must contain "nvidia,tegra30-pwm". Otherwise, must contain
6+
"nvidia,<chip>-pwm", plus one of the above, where <chip> is tegra114,
7+
tegra124, tegra132, or tegra210.
78
- reg: physical base address and length of the controller's registers
89
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
910
the cells format.

‎Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt

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77
Required properties:
88

9-
- compatible : should be "nvidia,tegra20-rtc".
9+
- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
10+
must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
11+
can be tegra30, tegra114, tegra124, or tegra132.
1012
- reg : Specifies base physical address and size of the registers.
1113
- interrupts : A single interrupt specifier.
1214
- clocks : Must contain one entry, for the module clock.

‎Documentation/devicetree/bindings/serial/of-serial.txt

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@@ -8,7 +8,10 @@ Required properties:
88
- "ns16550"
99
- "ns16750"
1010
- "ns16850"
11-
- "nvidia,tegra20-uart"
11+
- For Tegra20, must contain "nvidia,tegra20-uart"
12+
- For other Tegra, must contain '"nvidia,<chip>-uart",
13+
"nvidia,tegra20-uart"' where <chip> is tegra30, tegra114, tegra124,
14+
tegra132, or tegra210.
1215
- "nxp,lpc3220-uart"
1316
- "ralink,rt2880-uart"
1417
- "ibm,qpace-nwp-serial"

‎Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt

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11
NVIDIA Tegra30 AHUB (Audio Hub)
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33
Required properties:
4-
- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc.
4+
- compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5+
must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6+
"nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
7+
plus at least one of the above, where <chip> is tegra132.
58
- reg : Should contain the register physical address and length for each of
69
the AHUB's register blocks.
710
- Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.

‎Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt

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11
NVIDIA Tegra30 HDA controller
22

33
Required properties:
4-
- compatible : "nvidia,tegra30-hda"
4+
- compatible : For Tegra30, must contain "nvidia,tegra30-hda". Otherwise,
5+
must contain '"nvidia,<chip>-hda", "nvidia,tegra30-hda"', where <chip> is
6+
tegra114, tegra124, or tegra132.
57
- reg : Should contain the HDA registers location and length.
68
- interrupts : The interrupt from the HDA controller.
79
- clocks : Must contain an entry for each required entry in clock-names.

‎Documentation/devicetree/bindings/sound/nvidia,tegra30-i2s.txt

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11
NVIDIA Tegra30 I2S controller
22

33
Required properties:
4-
- compatible : "nvidia,tegra30-i2s"
4+
- compatible : For Tegra30, must contain "nvidia,tegra30-i2s". For Tegra124,
5+
must contain "nvidia,tegra124-i2s". Otherwise, must contain
6+
"nvidia,<chip>-i2s" plus at least one of the above, where <chip> is
7+
tegra114 or tegra132.
58
- reg : Should contain I2S registers location and length
69
- clocks : Must contain one entry, for the module clock.
710
See ../clocks/clock-bindings.txt for details.

‎Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt

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11
NVIDIA Tegra114 SPI controller.
22

33
Required properties:
4-
- compatible : should be "nvidia,tegra114-spi".
4+
- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5+
Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
6+
<chip> is tegra124, tegra132, or tegra210.
57
- reg: Should contain SPI registers location and length.
68
- interrupts: Should contain SPI interrupts.
79
- clock-names : Must include the following entries:

‎Documentation/devicetree/bindings/submitting-patches.txt

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@@ -15,6 +15,29 @@ I. For patch submitters
1515
3) The Documentation/ portion of the patch should come in the series before
1616
the code implementing the binding.
1717

18+
4) Any compatible strings used in a chip or board DTS file must be
19+
previously documented in the corresponding DT binding text file
20+
in Documentation/devicetree/bindings. This rule applies even if
21+
the Linux device driver does not yet match on the compatible
22+
string. [ checkpatch will emit warnings if this step is not
23+
followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864
24+
("checkpatch: add DT compatible string documentation checks"). ]
25+
26+
5) The wildcard "<chip>" may be used in compatible strings, as in
27+
the following example:
28+
29+
- compatible: Must contain '"nvidia,<chip>-pcie",
30+
"nvidia,tegra20-pcie"' where <chip> is tegra30, tegra132, ...
31+
32+
As in the above example, the known values of "<chip>" should be
33+
documented if it is used.
34+
35+
6) If a documented compatible string is not yet matched by the
36+
driver, the documentation should also include a compatible
37+
string that is matched by the driver (as in the "nvidia,tegra20-pcie"
38+
example above).
39+
40+
1841
II. For kernel maintainers
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2043
1) If you aren't comfortable reviewing a given binding, reply to it and ask

‎Documentation/devicetree/bindings/thermal/tegra-soctherm.txt

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@@ -7,7 +7,9 @@ notifications. It is also used to manage emergency shutdown in an
77
overheating situation.
88

99
Required properties :
10-
- compatible : "nvidia,tegra124-soctherm".
10+
- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11+
For Tegra132, must contain "nvidia,tegra132-soctherm".
12+
For Tegra210, must contain "nvidia,tegra210-soctherm".
1113
- reg : Should contain 1 entry:
1214
- SOCTHERM register set
1315
- interrupts : Defines the interrupt used by SOCTHERM

‎Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt

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@@ -6,7 +6,9 @@ trigger a legacy watchdog reset.
66

77
Required properties:
88

9-
- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
9+
- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise,
10+
must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where
11+
<chip> is tegra124 or tegra132.
1012
- reg : Specifies base physical address and size of the registers.
1113
- interrupts : A list of 6 interrupts; one per each of timer channels 1
1214
through 5, and one for the shared interrupt for the remaining channels.

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