|
| 1 | +/* |
| 2 | + * PowerNV cpuidle code |
| 3 | + * |
| 4 | + * Copyright 2015 IBM Corp. |
| 5 | + * |
| 6 | + * This program is free software; you can redistribute it and/or |
| 7 | + * modify it under the terms of the GNU General Public License |
| 8 | + * as published by the Free Software Foundation; either version |
| 9 | + * 2 of the License, or (at your option) any later version. |
| 10 | + */ |
| 11 | + |
| 12 | +#include <linux/types.h> |
| 13 | +#include <linux/mm.h> |
| 14 | +#include <linux/slab.h> |
| 15 | +#include <linux/of.h> |
| 16 | + |
| 17 | +#include <asm/firmware.h> |
| 18 | +#include <asm/opal.h> |
| 19 | +#include <asm/cputhreads.h> |
| 20 | +#include <asm/cpuidle.h> |
| 21 | +#include <asm/code-patching.h> |
| 22 | +#include <asm/smp.h> |
| 23 | + |
| 24 | +#include "powernv.h" |
| 25 | +#include "subcore.h" |
| 26 | + |
| 27 | +static u32 supported_cpuidle_states; |
| 28 | + |
| 29 | +int pnv_save_sprs_for_winkle(void) |
| 30 | +{ |
| 31 | + int cpu; |
| 32 | + int rc; |
| 33 | + |
| 34 | + /* |
| 35 | + * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric accross |
| 36 | + * all cpus at boot. Get these reg values of current cpu and use the |
| 37 | + * same accross all cpus. |
| 38 | + */ |
| 39 | + uint64_t lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1; |
| 40 | + uint64_t hid0_val = mfspr(SPRN_HID0); |
| 41 | + uint64_t hid1_val = mfspr(SPRN_HID1); |
| 42 | + uint64_t hid4_val = mfspr(SPRN_HID4); |
| 43 | + uint64_t hid5_val = mfspr(SPRN_HID5); |
| 44 | + uint64_t hmeer_val = mfspr(SPRN_HMEER); |
| 45 | + |
| 46 | + for_each_possible_cpu(cpu) { |
| 47 | + uint64_t pir = get_hard_smp_processor_id(cpu); |
| 48 | + uint64_t hsprg0_val = (uint64_t)&paca[cpu]; |
| 49 | + |
| 50 | + /* |
| 51 | + * HSPRG0 is used to store the cpu's pointer to paca. Hence last |
| 52 | + * 3 bits are guaranteed to be 0. Program slw to restore HSPRG0 |
| 53 | + * with 63rd bit set, so that when a thread wakes up at 0x100 we |
| 54 | + * can use this bit to distinguish between fastsleep and |
| 55 | + * deep winkle. |
| 56 | + */ |
| 57 | + hsprg0_val |= 1; |
| 58 | + |
| 59 | + rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); |
| 60 | + if (rc != 0) |
| 61 | + return rc; |
| 62 | + |
| 63 | + rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); |
| 64 | + if (rc != 0) |
| 65 | + return rc; |
| 66 | + |
| 67 | + /* HIDs are per core registers */ |
| 68 | + if (cpu_thread_in_core(cpu) == 0) { |
| 69 | + |
| 70 | + rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); |
| 71 | + if (rc != 0) |
| 72 | + return rc; |
| 73 | + |
| 74 | + rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); |
| 75 | + if (rc != 0) |
| 76 | + return rc; |
| 77 | + |
| 78 | + rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); |
| 79 | + if (rc != 0) |
| 80 | + return rc; |
| 81 | + |
| 82 | + rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); |
| 83 | + if (rc != 0) |
| 84 | + return rc; |
| 85 | + |
| 86 | + rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); |
| 87 | + if (rc != 0) |
| 88 | + return rc; |
| 89 | + } |
| 90 | + } |
| 91 | + |
| 92 | + return 0; |
| 93 | +} |
| 94 | + |
| 95 | +static void pnv_alloc_idle_core_states(void) |
| 96 | +{ |
| 97 | + int i, j; |
| 98 | + int nr_cores = cpu_nr_cores(); |
| 99 | + u32 *core_idle_state; |
| 100 | + |
| 101 | + /* |
| 102 | + * core_idle_state - First 8 bits track the idle state of each thread |
| 103 | + * of the core. The 8th bit is the lock bit. Initially all thread bits |
| 104 | + * are set. They are cleared when the thread enters deep idle state |
| 105 | + * like sleep and winkle. Initially the lock bit is cleared. |
| 106 | + * The lock bit has 2 purposes |
| 107 | + * a. While the first thread is restoring core state, it prevents |
| 108 | + * other threads in the core from switching to process context. |
| 109 | + * b. While the last thread in the core is saving the core state, it |
| 110 | + * prevents a different thread from waking up. |
| 111 | + */ |
| 112 | + for (i = 0; i < nr_cores; i++) { |
| 113 | + int first_cpu = i * threads_per_core; |
| 114 | + int node = cpu_to_node(first_cpu); |
| 115 | + |
| 116 | + core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, node); |
| 117 | + *core_idle_state = PNV_CORE_IDLE_THREAD_BITS; |
| 118 | + |
| 119 | + for (j = 0; j < threads_per_core; j++) { |
| 120 | + int cpu = first_cpu + j; |
| 121 | + |
| 122 | + paca[cpu].core_idle_state_ptr = core_idle_state; |
| 123 | + paca[cpu].thread_idle_state = PNV_THREAD_RUNNING; |
| 124 | + paca[cpu].thread_mask = 1 << j; |
| 125 | + } |
| 126 | + } |
| 127 | + |
| 128 | + update_subcore_sibling_mask(); |
| 129 | + |
| 130 | + if (supported_cpuidle_states & OPAL_PM_WINKLE_ENABLED) |
| 131 | + pnv_save_sprs_for_winkle(); |
| 132 | +} |
| 133 | + |
| 134 | +u32 pnv_get_supported_cpuidle_states(void) |
| 135 | +{ |
| 136 | + return supported_cpuidle_states; |
| 137 | +} |
| 138 | +EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states); |
| 139 | + |
| 140 | +static int __init pnv_init_idle_states(void) |
| 141 | +{ |
| 142 | + struct device_node *power_mgt; |
| 143 | + int dt_idle_states; |
| 144 | + u32 *flags; |
| 145 | + int i; |
| 146 | + |
| 147 | + supported_cpuidle_states = 0; |
| 148 | + |
| 149 | + if (cpuidle_disable != IDLE_NO_OVERRIDE) |
| 150 | + goto out; |
| 151 | + |
| 152 | + if (!firmware_has_feature(FW_FEATURE_OPALv3)) |
| 153 | + goto out; |
| 154 | + |
| 155 | + power_mgt = of_find_node_by_path("/ibm,opal/power-mgt"); |
| 156 | + if (!power_mgt) { |
| 157 | + pr_warn("opal: PowerMgmt Node not found\n"); |
| 158 | + goto out; |
| 159 | + } |
| 160 | + dt_idle_states = of_property_count_u32_elems(power_mgt, |
| 161 | + "ibm,cpu-idle-state-flags"); |
| 162 | + if (dt_idle_states < 0) { |
| 163 | + pr_warn("cpuidle-powernv: no idle states found in the DT\n"); |
| 164 | + goto out; |
| 165 | + } |
| 166 | + |
| 167 | + flags = kzalloc(sizeof(*flags) * dt_idle_states, GFP_KERNEL); |
| 168 | + if (of_property_read_u32_array(power_mgt, |
| 169 | + "ibm,cpu-idle-state-flags", flags, dt_idle_states)) { |
| 170 | + pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n"); |
| 171 | + goto out_free; |
| 172 | + } |
| 173 | + |
| 174 | + for (i = 0; i < dt_idle_states; i++) |
| 175 | + supported_cpuidle_states |= flags[i]; |
| 176 | + |
| 177 | + if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { |
| 178 | + patch_instruction( |
| 179 | + (unsigned int *)pnv_fastsleep_workaround_at_entry, |
| 180 | + PPC_INST_NOP); |
| 181 | + patch_instruction( |
| 182 | + (unsigned int *)pnv_fastsleep_workaround_at_exit, |
| 183 | + PPC_INST_NOP); |
| 184 | + } |
| 185 | + pnv_alloc_idle_core_states(); |
| 186 | +out_free: |
| 187 | + kfree(flags); |
| 188 | +out: |
| 189 | + return 0; |
| 190 | +} |
| 191 | + |
| 192 | +subsys_initcall(pnv_init_idle_states); |
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