@@ -132,13 +132,21 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_list_func_capabilities = 0x000A ,
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i40e_aqc_opc_list_dev_capabilities = 0x000B ,
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+ /* Proxy commands */
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+ i40e_aqc_opc_set_proxy_config = 0x0104 ,
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+ i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105 ,
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+
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/* LAA */
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i40e_aqc_opc_mac_address_read = 0x0107 ,
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i40e_aqc_opc_mac_address_write = 0x0108 ,
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/* PXE */
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i40e_aqc_opc_clear_pxe_mode = 0x0110 ,
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+ /* WoL commands */
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+ i40e_aqc_opc_set_wol_filter = 0x0120 ,
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+ i40e_aqc_opc_get_wake_reason = 0x0121 ,
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+
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/* internal switch commands */
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i40e_aqc_opc_get_switch_config = 0x0200 ,
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i40e_aqc_opc_add_statistics = 0x0201 ,
@@ -177,6 +185,7 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_remove_control_packet_filter = 0x025B ,
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i40e_aqc_opc_add_cloud_filters = 0x025C ,
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i40e_aqc_opc_remove_cloud_filters = 0x025D ,
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+ i40e_aqc_opc_clear_wol_switch_filters = 0x025E ,
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i40e_aqc_opc_add_mirror_rule = 0x0260 ,
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i40e_aqc_opc_delete_mirror_rule = 0x0261 ,
@@ -563,6 +572,56 @@ struct i40e_aqc_clear_pxe {
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I40E_CHECK_CMD_LENGTH (i40e_aqc_clear_pxe );
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+ /* Set WoL Filter (0x0120) */
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+
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+ struct i40e_aqc_set_wol_filter {
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+ __le16 filter_index ;
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+ #define I40E_AQC_MAX_NUM_WOL_FILTERS 8
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+ #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
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+ #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
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+ I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
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+
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+ #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
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+ #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
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+ I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT)
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+ __le16 cmd_flags ;
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+ #define I40E_AQC_SET_WOL_FILTER 0x8000
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+ #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
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+ #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
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+ #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1
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+ __le16 valid_flags ;
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+ #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
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+ #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
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+ u8 reserved [2 ];
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+ __le32 address_high ;
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+ __le32 address_low ;
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+ };
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+
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+ I40E_CHECK_CMD_LENGTH (i40e_aqc_set_wol_filter );
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+
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+ struct i40e_aqc_set_wol_filter_data {
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+ u8 filter [128 ];
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+ u8 mask [16 ];
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+ };
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+
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+ I40E_CHECK_STRUCT_LEN (0x90 , i40e_aqc_set_wol_filter_data );
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+
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+ /* Get Wake Reason (0x0121) */
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+
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+ struct i40e_aqc_get_wake_reason_completion {
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+ u8 reserved_1 [2 ];
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+ __le16 wake_reason ;
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+ #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
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+ #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
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+ I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
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+ #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
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+ #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
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+ I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
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+ u8 reserved_2 [12 ];
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+ };
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+
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+ I40E_CHECK_CMD_LENGTH (i40e_aqc_get_wake_reason_completion );
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+
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/* Switch configuration commands (0x02xx) */
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/* Used by many indirect commands that only pass an seid and a buffer in the
@@ -645,6 +704,8 @@ struct i40e_aqc_set_port_parameters {
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#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
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#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
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__le16 bad_frame_vsi ;
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+ #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
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+ #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
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__le16 default_seid ; /* reserved for command */
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u8 reserved [10 ];
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};
@@ -696,6 +757,7 @@ I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
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/* Set Switch Configuration (direct 0x0205) */
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struct i40e_aqc_set_switch_config {
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__le16 flags ;
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+ /* flags used for both fields below */
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#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
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#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
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__le16 valid_flags ;
@@ -1844,11 +1906,12 @@ struct i40e_aqc_get_link_status {
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#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
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#define I40E_AQ_CONFIG_CRC_ENA 0x04
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#define I40E_AQ_CONFIG_PACING_MASK 0x78
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- u8 external_power_ability ;
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+ u8 power_desc ;
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#define I40E_AQ_LINK_POWER_CLASS_1 0x00
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#define I40E_AQ_LINK_POWER_CLASS_2 0x01
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#define I40E_AQ_LINK_POWER_CLASS_3 0x02
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#define I40E_AQ_LINK_POWER_CLASS_4 0x03
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+ #define I40E_AQ_PWR_CLASS_MASK 0x03
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u8 reserved [4 ];
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};
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