|
96 | 96 | #size-cells = <1>;
|
97 | 97 | ranges;
|
98 | 98 |
|
99 |
| - misc_clk: misc_clk { |
100 |
| - compatible = "fixed-clock"; |
101 |
| - #clock-cells = <0>; |
102 |
| - clock-frequency = <25000000>; |
103 |
| - }; |
104 |
| - |
105 |
| - ttc0: timer@ff110000 { |
106 |
| - compatible = "cdns,ttc"; |
107 |
| - status = "disabled"; |
108 |
| - interrupt-parent = <&gic>; |
109 |
| - interrupts = <0 36 4>, <0 37 4>, <0 38 4>; |
110 |
| - reg = <0x0 0xff110000 0x1000>; |
111 |
| - clocks = <&misc_clk>; |
112 |
| - timer-width = <32>; |
113 |
| - }; |
114 |
| - |
115 |
| - ttc1: timer@ff120000 { |
116 |
| - compatible = "cdns,ttc"; |
117 |
| - status = "disabled"; |
118 |
| - interrupt-parent = <&gic>; |
119 |
| - interrupts = <0 39 4>, <0 40 4>, <0 41 4>; |
120 |
| - reg = <0x0 0xff120000 0x1000>; |
121 |
| - clocks = <&misc_clk>; |
122 |
| - timer-width = <32>; |
123 |
| - }; |
124 |
| - |
125 |
| - ttc2: timer@ff130000 { |
126 |
| - compatible = "cdns,ttc"; |
127 |
| - status = "disabled"; |
128 |
| - interrupt-parent = <&gic>; |
129 |
| - interrupts = <0 42 4>, <0 43 4>, <0 44 4>; |
130 |
| - reg = <0x0 0xff130000 0x1000>; |
131 |
| - clocks = <&misc_clk>; |
132 |
| - timer-width = <32>; |
133 |
| - }; |
134 |
| - |
135 |
| - ttc3: timer@ff140000 { |
136 |
| - compatible = "cdns,ttc"; |
| 99 | + can0: can@ff060000 { |
| 100 | + compatible = "xlnx,zynq-can-1.0"; |
137 | 101 | status = "disabled";
|
| 102 | + clocks = <&misc_clk &misc_clk>; |
| 103 | + clock-names = "can_clk", "pclk"; |
| 104 | + reg = <0x0 0xff060000 0x1000>; |
| 105 | + interrupts = <0 23 4>; |
138 | 106 | interrupt-parent = <&gic>;
|
139 |
| - interrupts = <0 45 4>, <0 46 4>, <0 47 4>; |
140 |
| - reg = <0x0 0xff140000 0x1000>; |
141 |
| - clocks = <&misc_clk>; |
142 |
| - timer-width = <32>; |
| 107 | + tx-fifo-depth = <0x40>; |
| 108 | + rx-fifo-depth = <0x40>; |
143 | 109 | };
|
144 | 110 |
|
145 |
| - uart0: serial@ff000000 { |
146 |
| - compatible = "cdns,uart-r1p8"; |
| 111 | + can1: can@ff070000 { |
| 112 | + compatible = "xlnx,zynq-can-1.0"; |
147 | 113 | status = "disabled";
|
148 |
| - interrupt-parent = <&gic>; |
149 |
| - interrupts = <0 21 4>; |
150 |
| - reg = <0x0 0xff000000 0x1000>; |
151 |
| - clock-names = "uart_clk", "pclk"; |
152 | 114 | clocks = <&misc_clk &misc_clk>;
|
| 115 | + clock-names = "can_clk", "pclk"; |
| 116 | + reg = <0x0 0xff070000 0x1000>; |
| 117 | + interrupts = <0 24 4>; |
| 118 | + interrupt-parent = <&gic>; |
| 119 | + tx-fifo-depth = <0x40>; |
| 120 | + rx-fifo-depth = <0x40>; |
153 | 121 | };
|
154 | 122 |
|
155 |
| - uart1: serial@ff010000 { |
156 |
| - compatible = "cdns,uart-r1p8"; |
157 |
| - status = "disabled"; |
158 |
| - interrupt-parent = <&gic>; |
159 |
| - interrupts = <0 22 4>; |
160 |
| - reg = <0x0 0xff010000 0x1000>; |
161 |
| - clock-names = "uart_clk", "pclk"; |
162 |
| - clocks = <&misc_clk &misc_clk>; |
| 123 | + misc_clk: misc_clk { |
| 124 | + compatible = "fixed-clock"; |
| 125 | + #clock-cells = <0>; |
| 126 | + clock-frequency = <25000000>; |
163 | 127 | };
|
164 | 128 |
|
165 | 129 | gpio: gpio@ff0a0000 {
|
166 |
| - compatible = "xlnx,zynq-gpio-1.0"; |
| 130 | + compatible = "xlnx,zynqmp-gpio-1.0"; |
167 | 131 | status = "disabled";
|
168 | 132 | #gpio-cells = <0x2>;
|
169 | 133 | clocks = <&misc_clk>;
|
|
220 | 184 | #size-cells = <0>;
|
221 | 185 | };
|
222 | 186 |
|
223 |
| - spi0: spi@ff040000 { |
224 |
| - compatible = "cdns,spi-r1p6"; |
225 |
| - status = "disabled"; |
226 |
| - interrupt-parent = <&gic>; |
227 |
| - interrupts = <0 19 4>; |
228 |
| - reg = <0x0 0xff040000 0x1000>; |
229 |
| - clock-names = "ref_clk", "pclk"; |
230 |
| - clocks = <&misc_clk &misc_clk>; |
231 |
| - #address-cells = <1>; |
232 |
| - #size-cells = <0>; |
233 |
| - }; |
234 |
| - |
235 |
| - spi1: spi@ff050000 { |
236 |
| - compatible = "cdns,spi-r1p6"; |
237 |
| - status = "disabled"; |
238 |
| - interrupt-parent = <&gic>; |
239 |
| - interrupts = <0 20 4>; |
240 |
| - reg = <0x0 0xff050000 0x1000>; |
241 |
| - clock-names = "ref_clk", "pclk"; |
242 |
| - clocks = <&misc_clk &misc_clk>; |
243 |
| - #address-cells = <1>; |
244 |
| - #size-cells = <0>; |
245 |
| - }; |
246 |
| - |
247 | 187 | i2c_clk: i2c_clk {
|
248 | 188 | compatible = "fixed-clock";
|
249 | 189 | #clock-cells = <0x0>;
|
|
272 | 212 | #size-cells = <0>;
|
273 | 213 | };
|
274 | 214 |
|
| 215 | + sata_clk: sata_clk { |
| 216 | + compatible = "fixed-clock"; |
| 217 | + #clock-cells = <0>; |
| 218 | + clock-frequency = <75000000>; |
| 219 | + }; |
| 220 | + |
| 221 | + sata: ahci@fd0c0000 { |
| 222 | + compatible = "ceva,ahci-1v84"; |
| 223 | + status = "disabled"; |
| 224 | + reg = <0x0 0xfd0c0000 0x2000>; |
| 225 | + interrupt-parent = <&gic>; |
| 226 | + interrupts = <0 133 4>; |
| 227 | + clocks = <&sata_clk>; |
| 228 | + }; |
| 229 | + |
275 | 230 | sdhci0: sdhci@ff160000 {
|
276 | 231 | compatible = "arasan,sdhci-8.9a";
|
277 | 232 | status = "disabled";
|
|
292 | 247 | clocks = <&misc_clk>, <&misc_clk>;
|
293 | 248 | };
|
294 | 249 |
|
| 250 | + smmu: smmu@fd800000 { |
| 251 | + compatible = "arm,mmu-500"; |
| 252 | + reg = <0x0 0xfd800000 0x20000>; |
| 253 | + #global-interrupts = <1>; |
| 254 | + interrupt-parent = <&gic>; |
| 255 | + interrupts = <0 157 4>, |
| 256 | + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, |
| 257 | + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, |
| 258 | + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>, |
| 259 | + <0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>; |
| 260 | + }; |
| 261 | + |
| 262 | + spi0: spi@ff040000 { |
| 263 | + compatible = "cdns,spi-r1p6"; |
| 264 | + status = "disabled"; |
| 265 | + interrupt-parent = <&gic>; |
| 266 | + interrupts = <0 19 4>; |
| 267 | + reg = <0x0 0xff040000 0x1000>; |
| 268 | + clock-names = "ref_clk", "pclk"; |
| 269 | + clocks = <&misc_clk &misc_clk>; |
| 270 | + #address-cells = <1>; |
| 271 | + #size-cells = <0>; |
| 272 | + }; |
| 273 | + |
| 274 | + spi1: spi@ff050000 { |
| 275 | + compatible = "cdns,spi-r1p6"; |
| 276 | + status = "disabled"; |
| 277 | + interrupt-parent = <&gic>; |
| 278 | + interrupts = <0 20 4>; |
| 279 | + reg = <0x0 0xff050000 0x1000>; |
| 280 | + clock-names = "ref_clk", "pclk"; |
| 281 | + clocks = <&misc_clk &misc_clk>; |
| 282 | + #address-cells = <1>; |
| 283 | + #size-cells = <0>; |
| 284 | + }; |
| 285 | + |
| 286 | + ttc0: timer@ff110000 { |
| 287 | + compatible = "cdns,ttc"; |
| 288 | + status = "disabled"; |
| 289 | + interrupt-parent = <&gic>; |
| 290 | + interrupts = <0 36 4>, <0 37 4>, <0 38 4>; |
| 291 | + reg = <0x0 0xff110000 0x1000>; |
| 292 | + clocks = <&misc_clk>; |
| 293 | + timer-width = <32>; |
| 294 | + }; |
| 295 | + |
| 296 | + ttc1: timer@ff120000 { |
| 297 | + compatible = "cdns,ttc"; |
| 298 | + status = "disabled"; |
| 299 | + interrupt-parent = <&gic>; |
| 300 | + interrupts = <0 39 4>, <0 40 4>, <0 41 4>; |
| 301 | + reg = <0x0 0xff120000 0x1000>; |
| 302 | + clocks = <&misc_clk>; |
| 303 | + timer-width = <32>; |
| 304 | + }; |
| 305 | + |
| 306 | + ttc2: timer@ff130000 { |
| 307 | + compatible = "cdns,ttc"; |
| 308 | + status = "disabled"; |
| 309 | + interrupt-parent = <&gic>; |
| 310 | + interrupts = <0 42 4>, <0 43 4>, <0 44 4>; |
| 311 | + reg = <0x0 0xff130000 0x1000>; |
| 312 | + clocks = <&misc_clk>; |
| 313 | + timer-width = <32>; |
| 314 | + }; |
| 315 | + |
| 316 | + ttc3: timer@ff140000 { |
| 317 | + compatible = "cdns,ttc"; |
| 318 | + status = "disabled"; |
| 319 | + interrupt-parent = <&gic>; |
| 320 | + interrupts = <0 45 4>, <0 46 4>, <0 47 4>; |
| 321 | + reg = <0x0 0xff140000 0x1000>; |
| 322 | + clocks = <&misc_clk>; |
| 323 | + timer-width = <32>; |
| 324 | + }; |
| 325 | + |
| 326 | + uart0: serial@ff000000 { |
| 327 | + compatible = "cdns,uart-r1p8"; |
| 328 | + status = "disabled"; |
| 329 | + interrupt-parent = <&gic>; |
| 330 | + interrupts = <0 21 4>; |
| 331 | + reg = <0x0 0xff000000 0x1000>; |
| 332 | + clock-names = "uart_clk", "pclk"; |
| 333 | + clocks = <&misc_clk &misc_clk>; |
| 334 | + }; |
| 335 | + |
| 336 | + uart1: serial@ff010000 { |
| 337 | + compatible = "cdns,uart-r1p8"; |
| 338 | + status = "disabled"; |
| 339 | + interrupt-parent = <&gic>; |
| 340 | + interrupts = <0 22 4>; |
| 341 | + reg = <0x0 0xff010000 0x1000>; |
| 342 | + clock-names = "uart_clk", "pclk"; |
| 343 | + clocks = <&misc_clk &misc_clk>; |
| 344 | + }; |
| 345 | + |
| 346 | + usb0: usb@fe200000 { |
| 347 | + compatible = "snps,dwc3"; |
| 348 | + status = "disabled"; |
| 349 | + interrupt-parent = <&gic>; |
| 350 | + interrupts = <0 65 4>; |
| 351 | + reg = <0x0 0xfe200000 0x40000>; |
| 352 | + clock-names = "clk_xin", "clk_ahb"; |
| 353 | + clocks = <&misc_clk>, <&misc_clk>; |
| 354 | + }; |
| 355 | + |
| 356 | + usb1: usb@fe300000 { |
| 357 | + compatible = "snps,dwc3"; |
| 358 | + status = "disabled"; |
| 359 | + interrupt-parent = <&gic>; |
| 360 | + interrupts = <0 70 4>; |
| 361 | + reg = <0x0 0xfe300000 0x40000>; |
| 362 | + clock-names = "clk_xin", "clk_ahb"; |
| 363 | + clocks = <&misc_clk>, <&misc_clk>; |
| 364 | + }; |
| 365 | + |
295 | 366 | watchdog0: watchdog@fd4d0000 {
|
296 | 367 | compatible = "cdns,wdt-r1p2";
|
297 | 368 | status = "disabled";
|
|
0 commit comments