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jgross1gregkh
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x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear
commit b2d7a07 upstream. Using only 32-bit writes for the pte will result in an intermediate L1TF vulnerable PTE. When running as a Xen PV guest this will at once switch the guest to shadow mode resulting in a loss of performance. Use arch_atomic64_xchg() instead which will perform the requested operation atomically with all 64 bits. Some performance considerations according to: https://software.intel.com/sites/default/files/managed/ad/dc/Intel-Xeon-Scalable-Processor-throughput-latency.pdf The main number should be the latency, as there is no tight loop around native_ptep_get_and_clear(). "lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a memory operand) isn't mentioned in that document. "lock xadd" (with xadd having 3 cycles less latency than xchg) has a latency of 11, so we can assume a latency of 14 for "lock xchg". Signed-off-by: Juergen Gross <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Reviewed-by: Jan Beulich <[email protected]> Tested-by: Jason Andryuk <[email protected]> Signed-off-by: Boris Ostrovsky <[email protected]> [ Atomic operations gained an arch_ prefix in 8bf705d ("locking/atomic/x86: Switch atomic.h to use atomic-instrumented.h") so s/arch_atomic64_xchg/atomic64_xchg/ for backport.] Signed-off-by: Jason Andryuk <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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arch/x86/include/asm/pgtable-3level.h

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@@ -2,6 +2,8 @@
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#ifndef _ASM_X86_PGTABLE_3LEVEL_H
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#define _ASM_X86_PGTABLE_3LEVEL_H
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#include <asm/atomic64_32.h>
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/*
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* Intel Physical Address Extension (PAE) Mode - three-level page
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* tables on PPro+ CPUs.
@@ -147,10 +149,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
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{
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pte_t res;
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/* xchg acts as a barrier before the setting of the high bits */
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res.pte_low = xchg(&ptep->pte_low, 0);
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res.pte_high = ptep->pte_high;
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ptep->pte_high = 0;
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res.pte = (pteval_t)atomic64_xchg((atomic64_t *)ptep, 0);
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return res;
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}

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