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atenartdavem330
atenart
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net: mvpp2: 1000baseX support
This patch adds the 1000Base-X PHY mode support in the Marvell PPv2 driver. 1000Base-X is quite close the SGMII and uses nearly the same code path. Signed-off-by: Antoine Tenart <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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  • drivers/net/ethernet/marvell

1 file changed

+51
-21
lines changed

‎drivers/net/ethernet/marvell/mvpp2.c

Lines changed: 51 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -4870,6 +4870,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
48704870
mvpp22_gop_init_rgmii(port);
48714871
break;
48724872
case PHY_INTERFACE_MODE_SGMII:
4873+
case PHY_INTERFACE_MODE_1000BASEX:
48734874
mvpp22_gop_init_sgmii(port);
48744875
break;
48754876
case PHY_INTERFACE_MODE_10GKR:
@@ -4907,7 +4908,8 @@ static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
49074908
u32 val;
49084909

49094910
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4910-
port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4911+
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
4912+
port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
49114913
/* Enable the GMAC link status irq for this port */
49124914
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
49134915
val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
@@ -4937,7 +4939,8 @@ static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
49374939
}
49384940

49394941
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4940-
port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4942+
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
4943+
port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
49414944
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
49424945
val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
49434946
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
@@ -4949,7 +4952,8 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
49494952
u32 val;
49504953

49514954
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
4952-
port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4955+
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
4956+
port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
49534957
val = readl(port->base + MVPP22_GMAC_INT_MASK);
49544958
val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
49554959
writel(val, port->base + MVPP22_GMAC_INT_MASK);
@@ -4974,6 +4978,7 @@ static int mvpp22_comphy_init(struct mvpp2_port *port)
49744978

49754979
switch (port->phy_interface) {
49764980
case PHY_INTERFACE_MODE_SGMII:
4981+
case PHY_INTERFACE_MODE_1000BASEX:
49774982
mode = PHY_MODE_SGMII;
49784983
break;
49794984
case PHY_INTERFACE_MODE_10GKR:
@@ -5056,7 +5061,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port,
50565061
else
50575062
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
50585063

5059-
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
5064+
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
5065+
port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
50605066
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
50615067
else
50625068
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -6266,7 +6272,8 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
62666272
link = true;
62676273
}
62686274
} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
6269-
port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
6275+
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
6276+
port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
62706277
val = readl(port->base + MVPP22_GMAC_INT_STAT);
62716278
if (val & MVPP22_GMAC_INT_STAT_LINK) {
62726279
event = true;
@@ -8032,20 +8039,25 @@ static void mvpp2_phylink_validate(struct net_device *dev,
80328039
phylink_set(mask, Pause);
80338040
phylink_set(mask, Asym_Pause);
80348041

8035-
phylink_set(mask, 10baseT_Half);
8036-
phylink_set(mask, 10baseT_Full);
8037-
phylink_set(mask, 100baseT_Half);
8038-
phylink_set(mask, 100baseT_Full);
8039-
phylink_set(mask, 1000baseT_Full);
8040-
phylink_set(mask, 10000baseT_Full);
8041-
8042-
if (state->interface == PHY_INTERFACE_MODE_10GKR) {
8042+
switch (state->interface) {
8043+
case PHY_INTERFACE_MODE_10GKR:
80438044
phylink_set(mask, 10000baseCR_Full);
80448045
phylink_set(mask, 10000baseSR_Full);
80458046
phylink_set(mask, 10000baseLR_Full);
80468047
phylink_set(mask, 10000baseLRM_Full);
80478048
phylink_set(mask, 10000baseER_Full);
80488049
phylink_set(mask, 10000baseKR_Full);
8050+
/* Fall-through */
8051+
default:
8052+
phylink_set(mask, 10baseT_Half);
8053+
phylink_set(mask, 10baseT_Full);
8054+
phylink_set(mask, 100baseT_Half);
8055+
phylink_set(mask, 100baseT_Full);
8056+
phylink_set(mask, 10000baseT_Full);
8057+
/* Fall-through */
8058+
case PHY_INTERFACE_MODE_1000BASEX:
8059+
phylink_set(mask, 1000baseT_Full);
8060+
phylink_set(mask, 1000baseX_Full);
80498061
}
80508062

80518063
bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
@@ -8084,12 +8096,18 @@ static void mvpp2_gmac_link_state(struct mvpp2_port *port,
80848096
state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
80858097
state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
80868098

8087-
if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
8099+
switch (port->phy_interface) {
8100+
case PHY_INTERFACE_MODE_1000BASEX:
80888101
state->speed = SPEED_1000;
8089-
else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
8090-
state->speed = SPEED_100;
8091-
else
8092-
state->speed = SPEED_10;
8102+
break;
8103+
default:
8104+
if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
8105+
state->speed = SPEED_1000;
8106+
else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
8107+
state->speed = SPEED_100;
8108+
else
8109+
state->speed = SPEED_10;
8110+
}
80938111

80948112
state->pause = 0;
80958113
if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
@@ -8181,8 +8199,18 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
81818199
ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
81828200
ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
81838201

8184-
if (!phy_interface_mode_is_rgmii(state->interface))
8202+
if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
8203+
/* 1000BaseX port cannot negotiate speed nor can it negotiate
8204+
* duplex: they are always operating with a fixed speed of
8205+
* 1000Mbps in full duplex, so force 1000 speed and full duplex
8206+
* here.
8207+
*/
8208+
ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
8209+
an |= MVPP2_GMAC_CONFIG_GMII_SPEED |
8210+
MVPP2_GMAC_CONFIG_FULL_DUPLEX;
8211+
} else if (!phy_interface_mode_is_rgmii(state->interface)) {
81858212
an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG;
8213+
}
81868214

81878215
if (state->duplex)
81888216
an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
@@ -8191,7 +8219,8 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
81918219
if (phylink_test(state->advertising, Asym_Pause))
81928220
an |= MVPP2_GMAC_FC_ADV_ASM_EN;
81938221

8194-
if (state->interface == PHY_INTERFACE_MODE_SGMII) {
8222+
if (state->interface == PHY_INTERFACE_MODE_SGMII ||
8223+
state->interface == PHY_INTERFACE_MODE_1000BASEX) {
81958224
an |= MVPP2_GMAC_IN_BAND_AUTONEG;
81968225
ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
81978226

@@ -8256,7 +8285,8 @@ static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
82568285
if (state->interface == PHY_INTERFACE_MODE_10GKR)
82578286
mvpp2_xlg_config(port, mode, state);
82588287
else if (phy_interface_mode_is_rgmii(state->interface) ||
8259-
state->interface == PHY_INTERFACE_MODE_SGMII)
8288+
state->interface == PHY_INTERFACE_MODE_SGMII ||
8289+
state->interface == PHY_INTERFACE_MODE_1000BASEX)
82608290
mvpp2_gmac_config(port, mode, state);
82618291

82628292
if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)

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