Skip to content

Commit dac1f6a

Browse files
Srinivas-Kandagatlavijay-suman
authored andcommitted
ASoC: codecs:lpass-wsa-macro: Fix vi feedback rate
commit d7bff1415e85b889dc8908be6aedba8807ae5e37 upstream. Currently the VI feedback rate is set to fixed 8K, fix this by getting the correct rate from params_rate. Without this patch incorrect rate will be set on the VI feedback recording resulting in rate miss match and audio artifacts. Fixes: 2c4066e ("ASoC: codecs: lpass-wsa-macro: add dapm widgets and route") Cc: [email protected] Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Mark Brown <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]> (cherry picked from commit 1a19d2306753a670ab19148317185c99b0b7c8c7) Signed-off-by: Vijayendra Suman <[email protected]>
1 parent 282ea03 commit dac1f6a

File tree

1 file changed

+36
-3
lines changed

1 file changed

+36
-3
lines changed

sound/soc/codecs/lpass-wsa-macro.c

Lines changed: 36 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,10 @@
6262
#define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0
6363
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0)
6464
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0
65+
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K 1
66+
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K 2
67+
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K 3
68+
#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K 4
6569
#define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248)
6670
#define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264)
6771
#define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268)
@@ -344,6 +348,7 @@ struct wsa_macro {
344348
int ear_spkr_gain;
345349
int spkr_gain_offset;
346350
int spkr_mode;
351+
u32 pcm_rate_vi;
347352
int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX];
348353
int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX];
349354
struct regmap *regmap;
@@ -967,6 +972,7 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
967972
struct snd_soc_dai *dai)
968973
{
969974
struct snd_soc_component *component = dai->component;
975+
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
970976
int ret;
971977

972978
switch (substream->stream) {
@@ -978,6 +984,11 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
978984
__func__, params_rate(params));
979985
return ret;
980986
}
987+
break;
988+
case SNDRV_PCM_STREAM_CAPTURE:
989+
if (dai->id == WSA_MACRO_AIF_VI)
990+
wsa->pcm_rate_vi = params_rate(params);
991+
981992
break;
982993
default:
983994
break;
@@ -1152,6 +1163,28 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
11521163
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
11531164
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
11541165
u32 tx_reg0, tx_reg1;
1166+
u32 rate_val;
1167+
1168+
switch (wsa->pcm_rate_vi) {
1169+
case 8000:
1170+
rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K;
1171+
break;
1172+
case 16000:
1173+
rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K;
1174+
break;
1175+
case 24000:
1176+
rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K;
1177+
break;
1178+
case 32000:
1179+
rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K;
1180+
break;
1181+
case 48000:
1182+
rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K;
1183+
break;
1184+
default:
1185+
rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K;
1186+
break;
1187+
}
11551188

11561189
if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
11571190
tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL;
@@ -1163,7 +1196,7 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
11631196

11641197
switch (event) {
11651198
case SND_SOC_DAPM_POST_PMU:
1166-
/* Enable V&I sensing */
1199+
/* Enable V&I sensing */
11671200
snd_soc_component_update_bits(component, tx_reg0,
11681201
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
11691202
CDC_WSA_TX_SPKR_PROT_RESET);
@@ -1172,10 +1205,10 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
11721205
CDC_WSA_TX_SPKR_PROT_RESET);
11731206
snd_soc_component_update_bits(component, tx_reg0,
11741207
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1175-
CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
1208+
rate_val);
11761209
snd_soc_component_update_bits(component, tx_reg1,
11771210
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1178-
CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
1211+
rate_val);
11791212
snd_soc_component_update_bits(component, tx_reg0,
11801213
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
11811214
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);

0 commit comments

Comments
 (0)