Skip to content

Commit db0aeb3

Browse files
davem330davem330
committed
Merge branch 'qed-Add-support-for-new-multi-partitioning-modes'
Sudarsana Reddy Kalluru says: ==================== qed*: Add support for new multi partitioning modes. The patch series simplifies the multi function (MF) mode implementation of qed/qede drivers, and adds support for new MF modes. Please consider applying it to net-next branch. ==================== Signed-off-by: David S. Miller <[email protected]>
2 parents 3a443bd + cac6f69 commit db0aeb3

File tree

17 files changed

+389
-82
lines changed

17 files changed

+389
-82
lines changed

‎drivers/net/ethernet/qlogic/qed/qed.h

Lines changed: 57 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -439,6 +439,59 @@ struct qed_fw_data {
439439
u32 init_ops_size;
440440
};
441441

442+
enum qed_mf_mode_bit {
443+
/* Supports PF-classification based on tag */
444+
QED_MF_OVLAN_CLSS,
445+
446+
/* Supports PF-classification based on MAC */
447+
QED_MF_LLH_MAC_CLSS,
448+
449+
/* Supports PF-classification based on protocol type */
450+
QED_MF_LLH_PROTO_CLSS,
451+
452+
/* Requires a default PF to be set */
453+
QED_MF_NEED_DEF_PF,
454+
455+
/* Allow LL2 to multicast/broadcast */
456+
QED_MF_LL2_NON_UNICAST,
457+
458+
/* Allow Cross-PF [& child VFs] Tx-switching */
459+
QED_MF_INTER_PF_SWITCH,
460+
461+
/* Unified Fabtic Port support enabled */
462+
QED_MF_UFP_SPECIFIC,
463+
464+
/* Disable Accelerated Receive Flow Steering (aRFS) */
465+
QED_MF_DISABLE_ARFS,
466+
467+
/* Use vlan for steering */
468+
QED_MF_8021Q_TAGGING,
469+
470+
/* Use stag for steering */
471+
QED_MF_8021AD_TAGGING,
472+
473+
/* Allow DSCP to TC mapping */
474+
QED_MF_DSCP_TO_TC_MAP,
475+
};
476+
477+
enum qed_ufp_mode {
478+
QED_UFP_MODE_ETS,
479+
QED_UFP_MODE_VNIC_BW,
480+
QED_UFP_MODE_UNKNOWN
481+
};
482+
483+
enum qed_ufp_pri_type {
484+
QED_UFP_PRI_OS,
485+
QED_UFP_PRI_VNIC,
486+
QED_UFP_PRI_UNKNOWN
487+
};
488+
489+
struct qed_ufp_info {
490+
enum qed_ufp_pri_type pri_type;
491+
enum qed_ufp_mode mode;
492+
u8 tc;
493+
};
494+
442495
enum BAR_ID {
443496
BAR_ID_0, /* used for GRC */
444497
BAR_ID_1 /* Used for doorbells */
@@ -547,6 +600,8 @@ struct qed_hwfn {
547600

548601
struct qed_dcbx_info *p_dcbx_info;
549602

603+
struct qed_ufp_info ufp_info;
604+
550605
struct qed_dmae_info dmae_info;
551606

552607
/* QM init */
@@ -669,10 +724,8 @@ struct qed_dev {
669724
u8 num_funcs_in_port;
670725

671726
u8 path_id;
672-
enum qed_mf_mode mf_mode;
673-
#define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
674-
#define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
675-
#define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
727+
728+
unsigned long mf_bits;
676729

677730
int pcie_width;
678731
int pcie_speed;

‎drivers/net/ethernet/qlogic/qed/qed_dcbx.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -274,15 +274,16 @@ qed_dcbx_process_tlv(struct qed_hwfn *p_hwfn,
274274
u32 pri_tc_tbl, int count, u8 dcbx_version)
275275
{
276276
enum dcbx_protocol_type type;
277+
bool enable, ieee, eth_tlv;
277278
u8 tc, priority_map;
278-
bool enable, ieee;
279279
u16 protocol_id;
280280
int priority;
281281
int i;
282282

283283
DP_VERBOSE(p_hwfn, QED_MSG_DCB, "Num APP entries = %d\n", count);
284284

285285
ieee = (dcbx_version == DCBX_CONFIG_VERSION_IEEE);
286+
eth_tlv = false;
286287
/* Parse APP TLV */
287288
for (i = 0; i < count; i++) {
288289
protocol_id = QED_MFW_GET_FIELD(p_tbl[i].entry,
@@ -304,13 +305,22 @@ qed_dcbx_process_tlv(struct qed_hwfn *p_hwfn,
304305
* indication, but we only got here if there was an
305306
* app tlv for the protocol, so dcbx must be enabled.
306307
*/
307-
enable = !(type == DCBX_PROTOCOL_ETH);
308+
if (type == DCBX_PROTOCOL_ETH) {
309+
enable = false;
310+
eth_tlv = true;
311+
} else {
312+
enable = true;
313+
}
308314

309315
qed_dcbx_update_app_info(p_data, p_hwfn, enable,
310316
priority, tc, type);
311317
}
312318
}
313319

320+
/* If Eth TLV is not detected, use UFP TC as default TC */
321+
if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits) && !eth_tlv)
322+
p_data->arr[DCBX_PROTOCOL_ETH].tc = p_hwfn->ufp_info.tc;
323+
314324
/* Update ramrod protocol data and hw_info fields
315325
* with default info when corresponding APP TLV's are not detected.
316326
* The enabled field has a different logic for ethernet as only for

‎drivers/net/ethernet/qlogic/qed/qed_dev.c

Lines changed: 78 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1149,18 +1149,10 @@ static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn)
11491149
return -EINVAL;
11501150
}
11511151

1152-
switch (p_hwfn->cdev->mf_mode) {
1153-
case QED_MF_DEFAULT:
1154-
case QED_MF_NPAR:
1155-
hw_mode |= 1 << MODE_MF_SI;
1156-
break;
1157-
case QED_MF_OVLAN:
1152+
if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits))
11581153
hw_mode |= 1 << MODE_MF_SD;
1159-
break;
1160-
default:
1161-
DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n");
1154+
else
11621155
hw_mode |= 1 << MODE_MF_SI;
1163-
}
11641156

11651157
hw_mode |= 1 << MODE_ASIC;
11661158

@@ -1507,6 +1499,11 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
15071499
STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);
15081500
STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,
15091501
p_hwfn->hw_info.ovlan);
1502+
1503+
DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
1504+
"Configuring LLH_FUNC_FILTER_HDR_SEL\n");
1505+
STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,
1506+
1);
15101507
}
15111508

15121509
/* Enable classification by MAC if needed */
@@ -1557,7 +1554,6 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
15571554

15581555
/* send function start command */
15591556
rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn,
1560-
p_hwfn->cdev->mf_mode,
15611557
allow_npar_tx_switch);
15621558
if (rc) {
15631559
DP_NOTICE(p_hwfn, "Function start ramrod failed\n");
@@ -1644,6 +1640,7 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
16441640
bool b_default_mtu = true;
16451641
struct qed_hwfn *p_hwfn;
16461642
int rc = 0, mfw_rc, i;
1643+
u16 ether_type;
16471644

16481645
if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) {
16491646
DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n");
@@ -1677,6 +1674,24 @@ int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params)
16771674
if (rc)
16781675
return rc;
16791676

1677+
if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING,
1678+
&cdev->mf_bits) ||
1679+
test_bit(QED_MF_8021AD_TAGGING,
1680+
&cdev->mf_bits))) {
1681+
if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits))
1682+
ether_type = ETH_P_8021Q;
1683+
else
1684+
ether_type = ETH_P_8021AD;
1685+
STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1686+
ether_type);
1687+
STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1688+
ether_type);
1689+
STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,
1690+
ether_type);
1691+
STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,
1692+
ether_type);
1693+
}
1694+
16801695
qed_fill_load_req_params(&load_req_params,
16811696
p_params->p_drv_load_params);
16821697
rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt,
@@ -2639,31 +2654,57 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
26392654
link->pause.autoneg,
26402655
p_caps->default_eee, p_caps->eee_lpi_timer);
26412656

2642-
/* Read Multi-function information from shmem */
2643-
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2644-
offsetof(struct nvm_cfg1, glob) +
2645-
offsetof(struct nvm_cfg1_glob, generic_cont0);
2657+
if (IS_LEAD_HWFN(p_hwfn)) {
2658+
struct qed_dev *cdev = p_hwfn->cdev;
26462659

2647-
generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
2660+
/* Read Multi-function information from shmem */
2661+
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
2662+
offsetof(struct nvm_cfg1, glob) +
2663+
offsetof(struct nvm_cfg1_glob, generic_cont0);
26482664

2649-
mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2650-
NVM_CFG1_GLOB_MF_MODE_OFFSET;
2665+
generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
26512666

2652-
switch (mf_mode) {
2653-
case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2654-
p_hwfn->cdev->mf_mode = QED_MF_OVLAN;
2655-
break;
2656-
case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2657-
p_hwfn->cdev->mf_mode = QED_MF_NPAR;
2658-
break;
2659-
case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2660-
p_hwfn->cdev->mf_mode = QED_MF_DEFAULT;
2661-
break;
2667+
mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >>
2668+
NVM_CFG1_GLOB_MF_MODE_OFFSET;
2669+
2670+
switch (mf_mode) {
2671+
case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED:
2672+
cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS);
2673+
break;
2674+
case NVM_CFG1_GLOB_MF_MODE_UFP:
2675+
cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2676+
BIT(QED_MF_LLH_PROTO_CLSS) |
2677+
BIT(QED_MF_UFP_SPECIFIC) |
2678+
BIT(QED_MF_8021Q_TAGGING);
2679+
break;
2680+
case NVM_CFG1_GLOB_MF_MODE_BD:
2681+
cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) |
2682+
BIT(QED_MF_LLH_PROTO_CLSS) |
2683+
BIT(QED_MF_8021AD_TAGGING);
2684+
break;
2685+
case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
2686+
cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2687+
BIT(QED_MF_LLH_PROTO_CLSS) |
2688+
BIT(QED_MF_LL2_NON_UNICAST) |
2689+
BIT(QED_MF_INTER_PF_SWITCH);
2690+
break;
2691+
case NVM_CFG1_GLOB_MF_MODE_DEFAULT:
2692+
cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) |
2693+
BIT(QED_MF_LLH_PROTO_CLSS) |
2694+
BIT(QED_MF_LL2_NON_UNICAST);
2695+
if (QED_IS_BB(p_hwfn->cdev))
2696+
cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF);
2697+
break;
2698+
}
2699+
2700+
DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2701+
cdev->mf_bits);
26622702
}
2663-
DP_INFO(p_hwfn, "Multi function mode is %08x\n",
2664-
p_hwfn->cdev->mf_mode);
26652703

2666-
/* Read Multi-function information from shmem */
2704+
DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
2705+
p_hwfn->cdev->mf_bits);
2706+
2707+
/* Read device capabilities information from shmem */
26672708
addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
26682709
offsetof(struct nvm_cfg1, glob) +
26692710
offsetof(struct nvm_cfg1_glob, device_capabilities);
@@ -2856,6 +2897,8 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
28562897
qed_mcp_cmd_port_init(p_hwfn, p_ptt);
28572898

28582899
qed_get_eee_caps(p_hwfn, p_ptt);
2900+
2901+
qed_mcp_read_ufp_config(p_hwfn, p_ptt);
28592902
}
28602903

28612904
if (qed_mcp_is_init(p_hwfn)) {
@@ -3462,7 +3505,7 @@ int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn,
34623505
u32 high = 0, low = 0, en;
34633506
int i;
34643507

3465-
if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3508+
if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
34663509
return 0;
34673510

34683511
qed_llh_mac_to_filter(&high, &low, p_filter);
@@ -3507,7 +3550,7 @@ void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn,
35073550
u32 high = 0, low = 0;
35083551
int i;
35093552

3510-
if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3553+
if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits))
35113554
return;
35123555

35133556
qed_llh_mac_to_filter(&high, &low, p_filter);
@@ -3549,7 +3592,7 @@ qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn,
35493592
u32 high = 0, low = 0, en;
35503593
int i;
35513594

3552-
if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3595+
if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
35533596
return 0;
35543597

35553598
switch (type) {
@@ -3647,7 +3690,7 @@ qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn,
36473690
u32 high = 0, low = 0;
36483691
int i;
36493692

3650-
if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))
3693+
if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits))
36513694
return;
36523695

36533696
switch (type) {

‎drivers/net/ethernet/qlogic/qed/qed_fcoe.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -313,6 +313,9 @@ qed_sp_fcoe_conn_offload(struct qed_hwfn *p_hwfn,
313313
p_data->d_id.addr_mid = p_conn->d_id.addr_mid;
314314
p_data->d_id.addr_lo = p_conn->d_id.addr_lo;
315315
p_data->flags = p_conn->flags;
316+
if (test_bit(QED_MF_UFP_SPECIFIC, &p_hwfn->cdev->mf_bits))
317+
SET_FIELD(p_data->flags,
318+
FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN, 1);
316319
p_data->def_q_idx = p_conn->def_q_idx;
317320

318321
return qed_spq_post(p_hwfn, p_ent, NULL);

‎drivers/net/ethernet/qlogic/qed/qed_hsi.h

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11993,6 +11993,16 @@ struct public_port {
1199311993
#define EEE_REMOTE_TW_TX_OFFSET 0
1199411994
#define EEE_REMOTE_TW_RX_MASK 0xffff0000
1199511995
#define EEE_REMOTE_TW_RX_OFFSET 16
11996+
11997+
u32 oem_cfg_port;
11998+
#define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003
11999+
#define OEM_CFG_CHANNEL_TYPE_OFFSET 0
12000+
#define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1
12001+
#define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2
12002+
#define OEM_CFG_SCHED_TYPE_MASK 0x0000000C
12003+
#define OEM_CFG_SCHED_TYPE_OFFSET 2
12004+
#define OEM_CFG_SCHED_TYPE_ETS 0x1
12005+
#define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2
1199612006
};
1199712007

1199812008
struct public_func {
@@ -12069,6 +12079,23 @@ struct public_func {
1206912079
#define DRV_ID_DRV_INIT_HW_MASK 0x80000000
1207012080
#define DRV_ID_DRV_INIT_HW_SHIFT 31
1207112081
#define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT)
12082+
12083+
u32 oem_cfg_func;
12084+
#define OEM_CFG_FUNC_TC_MASK 0x0000000F
12085+
#define OEM_CFG_FUNC_TC_OFFSET 0
12086+
#define OEM_CFG_FUNC_TC_0 0x0
12087+
#define OEM_CFG_FUNC_TC_1 0x1
12088+
#define OEM_CFG_FUNC_TC_2 0x2
12089+
#define OEM_CFG_FUNC_TC_3 0x3
12090+
#define OEM_CFG_FUNC_TC_4 0x4
12091+
#define OEM_CFG_FUNC_TC_5 0x5
12092+
#define OEM_CFG_FUNC_TC_6 0x6
12093+
#define OEM_CFG_FUNC_TC_7 0x7
12094+
12095+
#define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030
12096+
#define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4
12097+
#define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1
12098+
#define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2
1207212099
};
1207312100

1207412101
struct mcp_mac {
@@ -12495,6 +12522,7 @@ enum MFW_DRV_MSG_TYPE {
1249512522
MFW_DRV_MSG_BW_UPDATE10,
1249612523
MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
1249712524
MFW_DRV_MSG_BW_UPDATE11,
12525+
MFW_DRV_MSG_OEM_CFG_UPDATE,
1249812526
MFW_DRV_MSG_MAX
1249912527
};
1250012528

0 commit comments

Comments
 (0)