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Chin-Yen LeeKalle Valo
Chin-Yen Lee
authored and
Kalle Valo
committed
rtw89: use pci_read/write_config instead of dbi read/write
In the past we use dbi function of wifi mac to read/write pci config space, but the function will be remove in new chip. So use kernel api pci_read/write_config_byte instead. Signed-off-by: Chin-Yen Lee <[email protected]> Signed-off-by: Ping-Ke Shih <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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  • drivers/net/wireless/realtek/rtw89

1 file changed

+53
-75
lines changed

‎drivers/net/wireless/realtek/rtw89/pci.c

Lines changed: 53 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -1413,79 +1413,52 @@ static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u
14131413
return 0;
14141414
}
14151415

1416-
static int rtw89_dbi_write8(struct rtw89_dev *rtwdev, u16 addr, u8 data)
1416+
static int rtw89_pci_write_config_byte(struct rtw89_dev *rtwdev, u16 addr,
1417+
u8 data)
14171418
{
1418-
u16 write_addr;
1419-
u16 remainder = addr & ~(B_AX_DBI_ADDR_MSK | B_AX_DBI_WREN_MSK);
1420-
u8 flag;
1421-
int ret;
1422-
1423-
write_addr = addr & B_AX_DBI_ADDR_MSK;
1424-
write_addr |= u16_encode_bits(BIT(remainder), B_AX_DBI_WREN_MSK);
1425-
rtw89_write8(rtwdev, R_AX_DBI_WDATA + remainder, data);
1426-
rtw89_write16(rtwdev, R_AX_DBI_FLAG, write_addr);
1427-
rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_WFLAG >> 16);
1428-
1429-
ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10,
1430-
10 * RTW89_PCI_WR_RETRY_CNT, false,
1431-
rtwdev, R_AX_DBI_FLAG + 2);
1432-
if (ret)
1433-
WARN(flag, "failed to write to DBI register, addr=0x%04x\n",
1434-
addr);
1419+
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1420+
struct pci_dev *pdev = rtwpci->pdev;
14351421

1436-
return ret;
1422+
return pci_write_config_byte(pdev, addr, data);
14371423
}
14381424

1439-
static int rtw89_dbi_read8(struct rtw89_dev *rtwdev, u16 addr, u8 *value)
1425+
static int rtw89_pci_read_config_byte(struct rtw89_dev *rtwdev, u16 addr,
1426+
u8 *value)
14401427
{
1441-
u16 read_addr = addr & B_AX_DBI_ADDR_MSK;
1442-
u8 flag;
1443-
int ret;
1444-
1445-
rtw89_write16(rtwdev, R_AX_DBI_FLAG, read_addr);
1446-
rtw89_write8(rtwdev, R_AX_DBI_FLAG + 2, B_AX_DBI_RFLAG >> 16);
1447-
1448-
ret = read_poll_timeout_atomic(rtw89_read8, flag, !flag, 10,
1449-
10 * RTW89_PCI_WR_RETRY_CNT, false,
1450-
rtwdev, R_AX_DBI_FLAG + 2);
1451-
1452-
if (!ret) {
1453-
read_addr = R_AX_DBI_RDATA + (addr & 3);
1454-
*value = rtw89_read8(rtwdev, read_addr);
1455-
} else {
1456-
WARN(1, "failed to read DBI register, addr=0x%04x\n", addr);
1457-
ret = -EIO;
1458-
}
1428+
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
1429+
struct pci_dev *pdev = rtwpci->pdev;
14591430

1460-
return ret;
1431+
return pci_read_config_byte(pdev, addr, value);
14611432
}
14621433

1463-
static int rtw89_dbi_write8_set(struct rtw89_dev *rtwdev, u16 addr, u8 bit)
1434+
static int rtw89_pci_config_byte_set(struct rtw89_dev *rtwdev, u16 addr,
1435+
u8 bit)
14641436
{
14651437
u8 value;
14661438
int ret;
14671439

1468-
ret = rtw89_dbi_read8(rtwdev, addr, &value);
1440+
ret = rtw89_pci_read_config_byte(rtwdev, addr, &value);
14691441
if (ret)
14701442
return ret;
14711443

14721444
value |= bit;
1473-
ret = rtw89_dbi_write8(rtwdev, addr, value);
1445+
ret = rtw89_pci_write_config_byte(rtwdev, addr, value);
14741446

14751447
return ret;
14761448
}
14771449

1478-
static int rtw89_dbi_write8_clr(struct rtw89_dev *rtwdev, u16 addr, u8 bit)
1450+
static int rtw89_pci_config_byte_clr(struct rtw89_dev *rtwdev, u16 addr,
1451+
u8 bit)
14791452
{
14801453
u8 value;
14811454
int ret;
14821455

1483-
ret = rtw89_dbi_read8(rtwdev, addr, &value);
1456+
ret = rtw89_pci_read_config_byte(rtwdev, addr, &value);
14841457
if (ret)
14851458
return ret;
14861459

14871460
value &= ~bit;
1488-
ret = rtw89_dbi_write8(rtwdev, addr, value);
1461+
ret = rtw89_pci_write_config_byte(rtwdev, addr, value);
14891462

14901463
return ret;
14911464
}
@@ -1542,9 +1515,10 @@ static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en)
15421515
rtwdev->chip->chip_id == RTL8852C)
15431516
return 0;
15441517

1545-
ret = rtw89_dbi_read8(rtwdev, RTW89_PCIE_PHY_RATE, &val8);
1518+
ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_PHY_RATE, &val8);
15461519
if (ret) {
1547-
rtw89_err(rtwdev, "[ERR]dbi_r8_pcie %X\n", RTW89_PCIE_PHY_RATE);
1520+
rtw89_err(rtwdev, "[ERR]pci config read %X\n",
1521+
RTW89_PCIE_PHY_RATE);
15481522
return ret;
15491523
}
15501524

@@ -1557,17 +1531,18 @@ static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en)
15571531
return -EOPNOTSUPP;
15581532
}
15591533
/* Disable L1BD */
1560-
ret = rtw89_dbi_read8(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori);
1534+
ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori);
15611535
if (ret) {
1562-
rtw89_err(rtwdev, "[ERR]dbi_r8_pcie %X\n", RTW89_PCIE_L1_CTRL);
1536+
rtw89_err(rtwdev, "[ERR]pci config read %X\n", RTW89_PCIE_L1_CTRL);
15631537
return ret;
15641538
}
15651539

15661540
if (bdr_ori & RTW89_PCIE_BIT_L1) {
1567-
ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_L1_CTRL,
1568-
bdr_ori & ~RTW89_PCIE_BIT_L1);
1541+
ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL,
1542+
bdr_ori & ~RTW89_PCIE_BIT_L1);
15691543
if (ret) {
1570-
rtw89_err(rtwdev, "[ERR]dbi_w8_pcie %X\n", RTW89_PCIE_L1_CTRL);
1544+
rtw89_err(rtwdev, "[ERR]pci config write %X\n",
1545+
RTW89_PCIE_L1_CTRL);
15711546
return ret;
15721547
}
15731548
l1_flag = true;
@@ -1662,14 +1637,17 @@ static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en)
16621637
}
16631638

16641639
/* CLK delay = 0 */
1665-
ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_CLK_CTRL, PCIE_CLKDLY_HW_0);
1640+
ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL,
1641+
PCIE_CLKDLY_HW_0);
16661642

16671643
end:
16681644
/* Set L1BD to ori */
16691645
if (l1_flag) {
1670-
ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_L1_CTRL, bdr_ori);
1646+
ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL,
1647+
bdr_ori);
16711648
if (ret) {
1672-
rtw89_err(rtwdev, "[ERR]dbi_w8_pcie %X\n", RTW89_PCIE_L1_CTRL);
1649+
rtw89_err(rtwdev, "[ERR]pci config write %X\n",
1650+
RTW89_PCIE_L1_CTRL);
16731651
return ret;
16741652
}
16751653
}
@@ -2552,17 +2530,17 @@ static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable)
25522530
if (rtw89_pci_disable_clkreq)
25532531
return;
25542532

2555-
ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_CLK_CTRL,
2556-
PCIE_CLKDLY_HW_30US);
2533+
ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL,
2534+
PCIE_CLKDLY_HW_30US);
25572535
if (ret)
25582536
rtw89_err(rtwdev, "failed to set CLKREQ Delay\n");
25592537

25602538
if (enable)
2561-
ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_L1_CTRL,
2562-
RTW89_PCIE_BIT_CLK);
2539+
ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL,
2540+
RTW89_PCIE_BIT_CLK);
25632541
else
2564-
ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_L1_CTRL,
2565-
RTW89_PCIE_BIT_CLK);
2542+
ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL,
2543+
RTW89_PCIE_BIT_CLK);
25662544
if (ret)
25672545
rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d",
25682546
enable ? "set" : "unset", ret);
@@ -2576,24 +2554,24 @@ static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable)
25762554
if (rtw89_pci_disable_aspm_l1)
25772555
return;
25782556

2579-
ret = rtw89_dbi_read8(rtwdev, RTW89_PCIE_ASPM_CTRL, &value);
2557+
ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, &value);
25802558
if (ret)
25812559
rtw89_err(rtwdev, "failed to read ASPM Delay\n");
25822560

25832561
value &= ~(RTW89_L1DLY_MASK | RTW89_L0DLY_MASK);
25842562
value |= FIELD_PREP(RTW89_L1DLY_MASK, PCIE_L1DLY_16US) |
25852563
FIELD_PREP(RTW89_L0DLY_MASK, PCIE_L0SDLY_4US);
25862564

2587-
ret = rtw89_dbi_write8(rtwdev, RTW89_PCIE_ASPM_CTRL, value);
2565+
ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, value);
25882566
if (ret)
25892567
rtw89_err(rtwdev, "failed to read ASPM Delay\n");
25902568

25912569
if (enable)
2592-
ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_L1_CTRL,
2593-
RTW89_PCIE_BIT_L1);
2570+
ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_L1_CTRL,
2571+
RTW89_PCIE_BIT_L1);
25942572
else
2595-
ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_L1_CTRL,
2596-
RTW89_PCIE_BIT_L1);
2573+
ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1_CTRL,
2574+
RTW89_PCIE_BIT_L1);
25972575
if (ret)
25982576
rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d",
25992577
enable ? "set" : "unset", ret);
@@ -2657,11 +2635,11 @@ static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable)
26572635
int ret;
26582636

26592637
if (enable)
2660-
ret = rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_TIMER_CTRL,
2661-
RTW89_PCIE_BIT_L1SUB);
2638+
ret = rtw89_pci_config_byte_set(rtwdev, RTW89_PCIE_TIMER_CTRL,
2639+
RTW89_PCIE_BIT_L1SUB);
26622640
else
2663-
ret = rtw89_dbi_write8_clr(rtwdev, RTW89_PCIE_TIMER_CTRL,
2664-
RTW89_PCIE_BIT_L1SUB);
2641+
ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_TIMER_CTRL,
2642+
RTW89_PCIE_BIT_L1SUB);
26652643
if (ret)
26662644
rtw89_err(rtwdev, "failed to %s L1SS, ret=%d",
26672645
enable ? "set" : "unset", ret);
@@ -2878,10 +2856,10 @@ static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev)
28782856
return;
28792857

28802858
/* Hardware need write the reg twice to ensure the setting work */
2881-
rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_RST_MSTATE,
2882-
RTW89_PCIE_BIT_CFG_RST_MSTATE);
2883-
rtw89_dbi_write8_set(rtwdev, RTW89_PCIE_RST_MSTATE,
2884-
RTW89_PCIE_BIT_CFG_RST_MSTATE);
2859+
rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE,
2860+
RTW89_PCIE_BIT_CFG_RST_MSTATE);
2861+
rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_RST_MSTATE,
2862+
RTW89_PCIE_BIT_CFG_RST_MSTATE);
28852863
}
28862864

28872865
static int __maybe_unused rtw89_pci_resume(struct device *dev)

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