Skip to content

Commit db7c065

Browse files
author
Shawn Guo
committed
ARM: imx6sx: add BYPASS support for PLL clocks
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sx. Signed-off-by: Shawn Guo <[email protected]>
1 parent e90f419 commit db7c065

File tree

2 files changed

+78
-10
lines changed

2 files changed

+78
-10
lines changed

‎arch/arm/mach-imx/clk-imx6sx.c

Lines changed: 54 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,14 @@ static const char *lvds_sels[] = {
8181
"arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
8282
"dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
8383
};
84+
static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
85+
static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
86+
static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
87+
static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
88+
static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
89+
static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
90+
static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
91+
static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
8492

8593
static struct clk *clks[IMX6SX_CLK_CLK_END];
8694
static struct clk_onecell_data clk_data;
@@ -143,18 +151,54 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
143151
clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
144152
clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
145153

154+
/* Clock source from external clock via CLK1 PAD */
155+
clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
156+
146157
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
147158
base = of_iomap(np, 0);
148159
WARN_ON(!base);
149160

150-
/* type name parent_name base div_mask */
151-
clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
152-
clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
153-
clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
154-
clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
155-
clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
156-
clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
157-
clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3);
161+
clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
162+
clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
163+
clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
164+
clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
165+
clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
166+
clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
167+
clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
168+
169+
/* type name parent_name base div_mask */
170+
clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
171+
clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
172+
clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
173+
clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
174+
clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
175+
clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
176+
clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
177+
178+
clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
179+
clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
180+
clks[IMX6SX_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
181+
clks[IMX6SX_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
182+
clks[IMX6SX_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
183+
clks[IMX6SX_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
184+
clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
185+
186+
/* Do not bypass PLLs initially */
187+
clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);
188+
clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);
189+
clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);
190+
clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);
191+
clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);
192+
clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);
193+
clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);
194+
195+
clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
196+
clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
197+
clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
198+
clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
199+
clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
200+
clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
201+
clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0xe0, 13);
158202

159203
/*
160204
* Bit 20 is the reserved and read-only bit, we do this only for:
@@ -176,7 +220,8 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
176220
clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
177221
clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
178222

179-
clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);
223+
clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
224+
clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
180225

181226
clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
182227
base + 0xe0, 0, 2, 0, clk_enet_ref_table,

‎include/dt-bindings/clock/imx6sx-clock.h

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -251,6 +251,29 @@
251251
#define IMX6SX_CLK_SAI2_IPG 238
252252
#define IMX6SX_CLK_ESAI_IPG 239
253253
#define IMX6SX_CLK_ESAI_MEM 240
254-
#define IMX6SX_CLK_CLK_END 241
254+
#define IMX6SX_CLK_LVDS1_IN 241
255+
#define IMX6SX_CLK_ANACLK1 242
256+
#define IMX6SX_PLL1_BYPASS_SRC 243
257+
#define IMX6SX_PLL2_BYPASS_SRC 244
258+
#define IMX6SX_PLL3_BYPASS_SRC 245
259+
#define IMX6SX_PLL4_BYPASS_SRC 246
260+
#define IMX6SX_PLL5_BYPASS_SRC 247
261+
#define IMX6SX_PLL6_BYPASS_SRC 248
262+
#define IMX6SX_PLL7_BYPASS_SRC 249
263+
#define IMX6SX_CLK_PLL1 250
264+
#define IMX6SX_CLK_PLL2 251
265+
#define IMX6SX_CLK_PLL3 252
266+
#define IMX6SX_CLK_PLL4 253
267+
#define IMX6SX_CLK_PLL5 254
268+
#define IMX6SX_CLK_PLL6 255
269+
#define IMX6SX_CLK_PLL7 256
270+
#define IMX6SX_PLL1_BYPASS 257
271+
#define IMX6SX_PLL2_BYPASS 258
272+
#define IMX6SX_PLL3_BYPASS 259
273+
#define IMX6SX_PLL4_BYPASS 260
274+
#define IMX6SX_PLL5_BYPASS 261
275+
#define IMX6SX_PLL6_BYPASS 262
276+
#define IMX6SX_PLL7_BYPASS 263
277+
#define IMX6SX_CLK_CLK_END 264
255278

256279
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */

0 commit comments

Comments
 (0)