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#define SKX_UPI_PCI_PMON_CTL0 0x350
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#define SKX_UPI_PCI_PMON_CTR0 0x318
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#define SKX_UPI_PCI_PMON_BOX_CTL 0x378
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- #define SKX_PMON_CTL_UMASK_EXT 0xff
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+ #define SKX_UPI_CTL_UMASK_EXT 0xffefff
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/* SKX M2M */
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#define SKX_M2M_PCI_PMON_CTL0 0x228
@@ -328,7 +328,7 @@ DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6");
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DEFINE_UNCORE_FORMAT_ATTR (event_ext , event , "config:0-7,21" );
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DEFINE_UNCORE_FORMAT_ATTR (use_occ_ctr , use_occ_ctr , "config:7" );
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DEFINE_UNCORE_FORMAT_ATTR (umask , umask , "config:8-15" );
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- DEFINE_UNCORE_FORMAT_ATTR (umask_ext , umask , "config:8-15,32-39 " );
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+ DEFINE_UNCORE_FORMAT_ATTR (umask_ext , umask , "config:8-15,32-43,45-55 " );
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DEFINE_UNCORE_FORMAT_ATTR (qor , qor , "config:16" );
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DEFINE_UNCORE_FORMAT_ATTR (edge , edge , "config:18" );
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DEFINE_UNCORE_FORMAT_ATTR (tid_en , tid_en , "config:19" );
@@ -351,7 +351,6 @@ DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5");
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DEFINE_UNCORE_FORMAT_ATTR (filter_link , filter_link , "config1:5-8" );
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DEFINE_UNCORE_FORMAT_ATTR (filter_link2 , filter_link , "config1:6-8" );
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DEFINE_UNCORE_FORMAT_ATTR (filter_link3 , filter_link , "config1:12" );
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- DEFINE_UNCORE_FORMAT_ATTR (filter_link4 , filter_link , "config1:9-12" );
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DEFINE_UNCORE_FORMAT_ATTR (filter_nid , filter_nid , "config1:10-17" );
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DEFINE_UNCORE_FORMAT_ATTR (filter_nid2 , filter_nid , "config1:32-47" );
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DEFINE_UNCORE_FORMAT_ATTR (filter_state , filter_state , "config1:18-22" );
@@ -3302,7 +3301,6 @@ static struct attribute *skx_uncore_cha_formats_attr[] = {
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& format_attr_inv .attr ,
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& format_attr_thresh8 .attr ,
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& format_attr_filter_tid4 .attr ,
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- & format_attr_filter_link4 .attr ,
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& format_attr_filter_state5 .attr ,
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& format_attr_filter_rem .attr ,
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& format_attr_filter_loc .attr ,
@@ -3312,7 +3310,6 @@ static struct attribute *skx_uncore_cha_formats_attr[] = {
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& format_attr_filter_opc_0 .attr ,
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& format_attr_filter_opc_1 .attr ,
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& format_attr_filter_nc .attr ,
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- & format_attr_filter_c6 .attr ,
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& format_attr_filter_isoc .attr ,
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NULL ,
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};
@@ -3333,8 +3330,11 @@ static struct extra_reg skx_uncore_cha_extra_regs[] = {
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SNBEP_CBO_EVENT_EXTRA_REG (0x0534 , 0xffff , 0x4 ),
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SNBEP_CBO_EVENT_EXTRA_REG (0x0934 , 0xffff , 0x4 ),
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SNBEP_CBO_EVENT_EXTRA_REG (0x1134 , 0xffff , 0x4 ),
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- SNBEP_CBO_EVENT_EXTRA_REG (0x2134 , 0xffff , 0x4 ),
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- SNBEP_CBO_EVENT_EXTRA_REG (0x8134 , 0xffff , 0x4 ),
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+ SNBEP_CBO_EVENT_EXTRA_REG (0x3134 , 0xffff , 0x4 ),
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+ SNBEP_CBO_EVENT_EXTRA_REG (0x9134 , 0xffff , 0x4 ),
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+ SNBEP_CBO_EVENT_EXTRA_REG (0x35 , 0xff , 0x8 ),
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+ SNBEP_CBO_EVENT_EXTRA_REG (0x36 , 0xff , 0x8 ),
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+ EVENT_EXTRA_END
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};
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static u64 skx_cha_filter_mask (int fields )
@@ -3347,6 +3347,17 @@ static u64 skx_cha_filter_mask(int fields)
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mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LINK ;
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if (fields & 0x4 )
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mask |= SKX_CHA_MSR_PMON_BOX_FILTER_STATE ;
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+ if (fields & 0x8 ) {
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_REM ;
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_LOC ;
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC ;
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NM ;
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM ;
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC0 ;
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_OPC1 ;
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_NC ;
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+ mask |= SKX_CHA_MSR_PMON_BOX_FILTER_ISOC ;
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+ }
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return mask ;
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}
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@@ -3492,6 +3503,26 @@ static struct intel_uncore_type skx_uncore_irp = {
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.format_group = & skx_uncore_format_group ,
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};
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+ static struct attribute * skx_uncore_pcu_formats_attr [] = {
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+ & format_attr_event .attr ,
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+ & format_attr_umask .attr ,
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+ & format_attr_edge .attr ,
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+ & format_attr_inv .attr ,
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+ & format_attr_thresh8 .attr ,
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+ & format_attr_occ_invert .attr ,
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+ & format_attr_occ_edge_det .attr ,
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+ & format_attr_filter_band0 .attr ,
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+ & format_attr_filter_band1 .attr ,
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+ & format_attr_filter_band2 .attr ,
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+ & format_attr_filter_band3 .attr ,
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+ NULL ,
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+ };
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+
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+ static struct attribute_group skx_uncore_pcu_format_group = {
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+ .name = "format" ,
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+ .attrs = skx_uncore_pcu_formats_attr ,
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+ };
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+
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static struct intel_uncore_ops skx_uncore_pcu_ops = {
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IVBEP_UNCORE_MSR_OPS_COMMON_INIT (),
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.hw_config = hswep_pcu_hw_config ,
@@ -3510,7 +3541,7 @@ static struct intel_uncore_type skx_uncore_pcu = {
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.box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL ,
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.num_shared_regs = 1 ,
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.ops = & skx_uncore_pcu_ops ,
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- .format_group = & snbep_uncore_pcu_format_group ,
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+ .format_group = & skx_uncore_pcu_format_group ,
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};
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static struct intel_uncore_type * skx_msr_uncores [] = {
@@ -3603,8 +3634,8 @@ static struct intel_uncore_type skx_uncore_upi = {
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.perf_ctr_bits = 48 ,
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.perf_ctr = SKX_UPI_PCI_PMON_CTR0 ,
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.event_ctl = SKX_UPI_PCI_PMON_CTL0 ,
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- .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK ,
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- .event_mask_ext = SKX_PMON_CTL_UMASK_EXT ,
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+ .event_mask = SNBEP_PMON_RAW_EVENT_MASK ,
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+ .event_mask_ext = SKX_UPI_CTL_UMASK_EXT ,
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.box_ctl = SKX_UPI_PCI_PMON_BOX_CTL ,
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.ops = & skx_upi_uncore_pci_ops ,
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.format_group = & skx_upi_uncore_format_group ,
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