@@ -1886,32 +1886,31 @@ void sci_controller_power_control_queue_remove(struct isci_host *ihost,
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static void sci_controller_afe_initialization (struct isci_host * ihost )
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{
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const struct sci_oem_params * oem = & ihost -> oem_parameters ;
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+ struct pci_dev * pdev = ihost -> pdev ;
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u32 afe_status ;
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u32 phy_id ;
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/* Clear DFX Status registers */
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writel (0x0081000f , & ihost -> scu_registers -> afe .afe_dfx_master_control0 );
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udelay (AFE_REGISTER_WRITE_DELAY );
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- if (is_b0 ()) {
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+ if (is_b0 (pdev )) {
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/* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
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* Timer, PM Stagger Timer */
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writel (0x0007BFFF , & ihost -> scu_registers -> afe .afe_pmsn_master_control2 );
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udelay (AFE_REGISTER_WRITE_DELAY );
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}
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/* Configure bias currents to normal */
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- if (is_a0 ())
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- writel (0x00005500 , & ihost -> scu_registers -> afe .afe_bias_control );
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- else if (is_a2 ())
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+ if (is_a2 (pdev ))
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writel (0x00005A00 , & ihost -> scu_registers -> afe .afe_bias_control );
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- else if (is_b0 () || is_c0 ())
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+ else if (is_b0 (pdev ) || is_c0 (pdev ))
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writel (0x00005F00 , & ihost -> scu_registers -> afe .afe_bias_control );
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udelay (AFE_REGISTER_WRITE_DELAY );
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/* Enable PLL */
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- if (is_b0 () || is_c0 ())
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+ if (is_b0 (pdev ) || is_c0 (pdev ))
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writel (0x80040A08 , & ihost -> scu_registers -> afe .afe_pll_control0 );
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else
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writel (0x80040908 , & ihost -> scu_registers -> afe .afe_pll_control0 );
@@ -1924,7 +1923,7 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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udelay (AFE_REGISTER_WRITE_DELAY );
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} while ((afe_status & 0x00001000 ) == 0 );
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- if (is_a0 () || is_a2 ()) {
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+ if (is_a2 (pdev )) {
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/* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */
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writel (0x7bcc96ad , & ihost -> scu_registers -> afe .afe_pmsn_master_control0 );
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udelay (AFE_REGISTER_WRITE_DELAY );
@@ -1933,11 +1932,11 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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for (phy_id = 0 ; phy_id < SCI_MAX_PHYS ; phy_id ++ ) {
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const struct sci_phy_oem_params * oem_phy = & oem -> phys [phy_id ];
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- if (is_b0 ()) {
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+ if (is_b0 (pdev )) {
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/* Configure transmitter SSC parameters */
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writel (0x00030000 , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_tx_ssc_control );
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udelay (AFE_REGISTER_WRITE_DELAY );
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- } else if (is_c0 ()) {
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+ } else if (is_c0 (pdev )) {
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/* Configure transmitter SSC parameters */
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writel (0x0003000 , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_tx_ssc_control );
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udelay (AFE_REGISTER_WRITE_DELAY );
@@ -1961,11 +1960,9 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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/*
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* Power up TX and RX out from power down (PWRDNTX and PWRDNRX)
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* & increase TX int & ext bias 20%....(0xe85c) */
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- if (is_a0 ())
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- writel (0x000003D4 , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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- else if (is_a2 ())
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+ if (is_a2 (pdev ))
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writel (0x000003F0 , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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- else if (is_b0 ()) {
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+ else if (is_b0 (pdev )) {
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/* Power down TX and RX (PWRDNTX and PWRDNRX) */
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writel (0x000003D7 , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_channel_control );
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udelay (AFE_REGISTER_WRITE_DELAY );
@@ -1985,7 +1982,7 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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}
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udelay (AFE_REGISTER_WRITE_DELAY );
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- if (is_a0 () || is_a2 ()) {
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+ if (is_a2 (pdev )) {
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/* Enable TX equalization (0xe824) */
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writel (0x00040000 , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_tx_control );
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udelay (AFE_REGISTER_WRITE_DELAY );
@@ -1998,11 +1995,9 @@ static void sci_controller_afe_initialization(struct isci_host *ihost)
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udelay (AFE_REGISTER_WRITE_DELAY );
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/* Leave DFE/FFE on */
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- if (is_a0 ())
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- writel (0x3F09983F , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_rx_ssc_control0 );
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- else if (is_a2 ())
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+ if (is_a2 (pdev ))
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writel (0x3F11103F , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_rx_ssc_control0 );
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- else if (is_b0 ()) {
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+ else if (is_b0 (pdev )) {
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writel (0x3F11103F , & ihost -> scu_registers -> afe .scu_afe_xcvr [phy_id ].afe_rx_ssc_control0 );
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udelay (AFE_REGISTER_WRITE_DELAY );
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/* Enable TX equalization (0xe824) */
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