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17 | 17 |
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18 | 18 | #include "chip.h" |
19 | 19 |
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| 20 | +#define GLOBAL_STATUS 0x00 |
| 21 | +#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ |
| 22 | +#define GLOBAL_STATUS_PPU_STATE_MASK (0x3 << 14) /* 6165 6185 */ |
| 23 | +#define GLOBAL_STATUS_PPU_STATE_DISABLED_RST (0x0 << 14) |
| 24 | +#define GLOBAL_STATUS_PPU_STATE_INITIALIZING (0x1 << 14) |
| 25 | +#define GLOBAL_STATUS_PPU_STATE_DISABLED (0x2 << 14) |
| 26 | +#define GLOBAL_STATUS_PPU_STATE_POLLING (0x3 << 14) |
| 27 | +#define GLOBAL_STATUS_INIT_READY BIT(11) |
| 28 | +#define GLOBAL_STATUS_IRQ_AVB 8 |
| 29 | +#define GLOBAL_STATUS_IRQ_DEVICE 7 |
| 30 | +#define GLOBAL_STATUS_IRQ_STATS 6 |
| 31 | +#define GLOBAL_STATUS_IRQ_VTU_PROBLEM 5 |
| 32 | +#define GLOBAL_STATUS_IRQ_VTU_DONE 4 |
| 33 | +#define GLOBAL_STATUS_IRQ_ATU_PROBLEM 3 |
| 34 | +#define GLOBAL_STATUS_IRQ_ATU_DONE 2 |
| 35 | +#define GLOBAL_STATUS_IRQ_TCAM_DONE 1 |
| 36 | +#define GLOBAL_STATUS_IRQ_EEPROM_DONE 0 |
| 37 | +#define GLOBAL_MAC_01 0x01 |
| 38 | +#define GLOBAL_MAC_23 0x02 |
| 39 | +#define GLOBAL_MAC_45 0x03 |
| 40 | +#define GLOBAL_ATU_FID 0x01 |
| 41 | +#define GLOBAL_VTU_FID 0x02 |
| 42 | +#define GLOBAL_VTU_FID_MASK 0xfff |
| 43 | +#define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ |
| 44 | +#define GLOBAL_VTU_SID_MASK 0x3f |
| 45 | +#define GLOBAL_CONTROL 0x04 |
| 46 | +#define GLOBAL_CONTROL_SW_RESET BIT(15) |
| 47 | +#define GLOBAL_CONTROL_PPU_ENABLE BIT(14) |
| 48 | +#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ |
| 49 | +#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ |
| 50 | +#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ |
| 51 | +#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ |
| 52 | +#define GLOBAL_CONTROL_DEVICE_EN BIT(7) |
| 53 | +#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) |
| 54 | +#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) |
| 55 | +#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) |
| 56 | +#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) |
| 57 | +#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) |
| 58 | +#define GLOBAL_CONTROL_TCAM_EN BIT(1) |
| 59 | +#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) |
| 60 | +#define GLOBAL_VTU_OP 0x05 |
| 61 | +#define GLOBAL_VTU_OP_BUSY BIT(15) |
| 62 | +#define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) |
| 63 | +#define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) |
| 64 | +#define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) |
| 65 | +#define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) |
| 66 | +#define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) |
| 67 | +#define GLOBAL_VTU_VID 0x06 |
| 68 | +#define GLOBAL_VTU_VID_MASK 0xfff |
| 69 | +#define GLOBAL_VTU_VID_PAGE BIT(13) |
| 70 | +#define GLOBAL_VTU_VID_VALID BIT(12) |
| 71 | +#define GLOBAL_VTU_DATA_0_3 0x07 |
| 72 | +#define GLOBAL_VTU_DATA_4_7 0x08 |
| 73 | +#define GLOBAL_VTU_DATA_8_11 0x09 |
| 74 | +#define GLOBAL_VTU_STU_DATA_MASK 0x03 |
| 75 | +#define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 |
| 76 | +#define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 |
| 77 | +#define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 |
| 78 | +#define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 |
| 79 | +#define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 |
| 80 | +#define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 |
| 81 | +#define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 |
| 82 | +#define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 |
| 83 | +#define GLOBAL_ATU_CONTROL 0x0a |
| 84 | +#define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) |
| 85 | +#define GLOBAL_ATU_OP 0x0b |
| 86 | +#define GLOBAL_ATU_OP_BUSY BIT(15) |
| 87 | +#define GLOBAL_ATU_OP_NOP (0 << 12) |
| 88 | +#define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) |
| 89 | +#define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) |
| 90 | +#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) |
| 91 | +#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) |
| 92 | +#define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) |
| 93 | +#define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) |
| 94 | +#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) |
| 95 | +#define GLOBAL_ATU_DATA 0x0c |
| 96 | +#define GLOBAL_ATU_DATA_TRUNK BIT(15) |
| 97 | +#define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 |
| 98 | +#define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 |
| 99 | +#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 |
| 100 | +#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 |
| 101 | +#define GLOBAL_ATU_DATA_STATE_MASK 0x0f |
| 102 | +#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 |
| 103 | +#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d |
| 104 | +#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e |
| 105 | +#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f |
| 106 | +#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 |
| 107 | +#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 |
| 108 | +#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e |
| 109 | +#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f |
| 110 | +#define GLOBAL_ATU_MAC_01 0x0d |
| 111 | +#define GLOBAL_ATU_MAC_23 0x0e |
| 112 | +#define GLOBAL_ATU_MAC_45 0x0f |
| 113 | +#define GLOBAL_IP_PRI_0 0x10 |
| 114 | +#define GLOBAL_IP_PRI_1 0x11 |
| 115 | +#define GLOBAL_IP_PRI_2 0x12 |
| 116 | +#define GLOBAL_IP_PRI_3 0x13 |
| 117 | +#define GLOBAL_IP_PRI_4 0x14 |
| 118 | +#define GLOBAL_IP_PRI_5 0x15 |
| 119 | +#define GLOBAL_IP_PRI_6 0x16 |
| 120 | +#define GLOBAL_IP_PRI_7 0x17 |
| 121 | +#define GLOBAL_IEEE_PRI 0x18 |
| 122 | +#define GLOBAL_CORE_TAG_TYPE 0x19 |
| 123 | +#define GLOBAL_MONITOR_CONTROL 0x1a |
| 124 | +#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 |
| 125 | +#define GLOBAL_MONITOR_CONTROL_INGRESS_MASK (0xf << 12) |
| 126 | +#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 |
| 127 | +#define GLOBAL_MONITOR_CONTROL_EGRESS_MASK (0xf << 8) |
| 128 | +#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 |
| 129 | +#define GLOBAL_MONITOR_CONTROL_ARP_MASK (0xf << 4) |
| 130 | +#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 |
| 131 | +#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) |
| 132 | +#define GLOBAL_MONITOR_CONTROL_UPDATE BIT(15) |
| 133 | +#define GLOBAL_MONITOR_CONTROL_0180C280000000XLO (0x00 << 8) |
| 134 | +#define GLOBAL_MONITOR_CONTROL_0180C280000000XHI (0x01 << 8) |
| 135 | +#define GLOBAL_MONITOR_CONTROL_0180C280000002XLO (0x02 << 8) |
| 136 | +#define GLOBAL_MONITOR_CONTROL_0180C280000002XHI (0x03 << 8) |
| 137 | +#define GLOBAL_MONITOR_CONTROL_INGRESS (0x20 << 8) |
| 138 | +#define GLOBAL_MONITOR_CONTROL_EGRESS (0x21 << 8) |
| 139 | +#define GLOBAL_MONITOR_CONTROL_CPU_DEST (0x30 << 8) |
| 140 | +#define GLOBAL_CONTROL_2 0x1c |
| 141 | +#define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 |
| 142 | +#define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 |
| 143 | +#define GLOBAL_CONTROL_2_HIST_RX (0x1 << 6) |
| 144 | +#define GLOBAL_CONTROL_2_HIST_TX (0x2 << 6) |
| 145 | +#define GLOBAL_CONTROL_2_HIST_RX_TX (0x3 << 6) |
| 146 | +#define GLOBAL_STATS_OP 0x1d |
| 147 | +#define GLOBAL_STATS_OP_BUSY BIT(15) |
| 148 | +#define GLOBAL_STATS_OP_NOP (0 << 12) |
| 149 | +#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) |
| 150 | +#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) |
| 151 | +#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) |
| 152 | +#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) |
| 153 | +#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) |
| 154 | +#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) |
| 155 | +#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) |
| 156 | +#define GLOBAL_STATS_OP_BANK_1_BIT_9 BIT(9) |
| 157 | +#define GLOBAL_STATS_OP_BANK_1_BIT_10 BIT(10) |
| 158 | +#define GLOBAL_STATS_COUNTER_32 0x1e |
| 159 | +#define GLOBAL_STATS_COUNTER_01 0x1f |
| 160 | + |
20 | 161 | int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); |
21 | 162 | int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); |
22 | 163 | int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask); |
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