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maorgottliebSaeed Mahameed
maorgottlieb
authored and
Saeed Mahameed
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net/mlx5: Lag, set match mask according to the traffic type bitmap
Set the related bits in the match definer mask according to the TT mapping. This mask will be used to create the match definers. Signed-off-by: Maor Gottlieb <[email protected]> Reviewed-by: Mark Bloch <[email protected]> Signed-off-by: Saeed Mahameed <[email protected]>
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  • drivers/net/ethernet/mellanox/mlx5/core/lag

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‎drivers/net/ethernet/mellanox/mlx5/core/lag/port_sel.c

Lines changed: 182 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,188 @@
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#include <linux/netdevice.h>
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#include "lag.h"
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static int mlx5_lag_set_definer_inner(u32 *match_definer_mask,
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enum mlx5_traffic_types tt)
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{
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int format_id;
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u8 *ipv6;
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switch (tt) {
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case MLX5_TT_IPV4_UDP:
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case MLX5_TT_IPV4_TCP:
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format_id = 23;
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_l4_sport);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_l4_dport);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_ip_src_addr);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_ip_dest_addr);
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break;
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case MLX5_TT_IPV4:
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format_id = 23;
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_l3_type);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_dmac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_dmac_15_0);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_smac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_smac_15_0);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_ip_src_addr);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_ip_dest_addr);
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break;
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case MLX5_TT_IPV6_TCP:
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case MLX5_TT_IPV6_UDP:
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format_id = 31;
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MLX5_SET_TO_ONES(match_definer_format_31, match_definer_mask,
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inner_l4_sport);
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MLX5_SET_TO_ONES(match_definer_format_31, match_definer_mask,
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inner_l4_dport);
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ipv6 = MLX5_ADDR_OF(match_definer_format_31, match_definer_mask,
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inner_ip_dest_addr);
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memset(ipv6, 0xff, 16);
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ipv6 = MLX5_ADDR_OF(match_definer_format_31, match_definer_mask,
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inner_ip_src_addr);
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memset(ipv6, 0xff, 16);
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break;
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case MLX5_TT_IPV6:
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format_id = 32;
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ipv6 = MLX5_ADDR_OF(match_definer_format_32, match_definer_mask,
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inner_ip_dest_addr);
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memset(ipv6, 0xff, 16);
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ipv6 = MLX5_ADDR_OF(match_definer_format_32, match_definer_mask,
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inner_ip_src_addr);
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memset(ipv6, 0xff, 16);
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MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
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inner_dmac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
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inner_dmac_15_0);
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MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
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inner_smac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_32, match_definer_mask,
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inner_smac_15_0);
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break;
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default:
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format_id = 23;
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_l3_type);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_dmac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_dmac_15_0);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_smac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_23, match_definer_mask,
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inner_smac_15_0);
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break;
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}
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89+
return format_id;
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}
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static int mlx5_lag_set_definer(u32 *match_definer_mask,
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enum mlx5_traffic_types tt, bool tunnel,
94+
enum netdev_lag_hash hash)
95+
{
96+
int format_id;
97+
u8 *ipv6;
98+
99+
if (tunnel)
100+
return mlx5_lag_set_definer_inner(match_definer_mask, tt);
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switch (tt) {
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case MLX5_TT_IPV4_UDP:
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case MLX5_TT_IPV4_TCP:
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format_id = 22;
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
107+
outer_l4_sport);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_l4_dport);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_ip_src_addr);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_ip_dest_addr);
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break;
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case MLX5_TT_IPV4:
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format_id = 22;
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_l3_type);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_dmac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_dmac_15_0);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_smac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_smac_15_0);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_ip_src_addr);
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MLX5_SET_TO_ONES(match_definer_format_22, match_definer_mask,
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outer_ip_dest_addr);
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break;
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case MLX5_TT_IPV6_TCP:
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case MLX5_TT_IPV6_UDP:
134+
format_id = 29;
135+
MLX5_SET_TO_ONES(match_definer_format_29, match_definer_mask,
136+
outer_l4_sport);
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MLX5_SET_TO_ONES(match_definer_format_29, match_definer_mask,
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outer_l4_dport);
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ipv6 = MLX5_ADDR_OF(match_definer_format_29, match_definer_mask,
140+
outer_ip_dest_addr);
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memset(ipv6, 0xff, 16);
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ipv6 = MLX5_ADDR_OF(match_definer_format_29, match_definer_mask,
143+
outer_ip_src_addr);
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memset(ipv6, 0xff, 16);
145+
break;
146+
case MLX5_TT_IPV6:
147+
format_id = 30;
148+
ipv6 = MLX5_ADDR_OF(match_definer_format_30, match_definer_mask,
149+
outer_ip_dest_addr);
150+
memset(ipv6, 0xff, 16);
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ipv6 = MLX5_ADDR_OF(match_definer_format_30, match_definer_mask,
152+
outer_ip_src_addr);
153+
memset(ipv6, 0xff, 16);
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MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
155+
outer_dmac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
157+
outer_dmac_15_0);
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MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
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outer_smac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_30, match_definer_mask,
161+
outer_smac_15_0);
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break;
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default:
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format_id = 0;
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MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
166+
outer_smac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
168+
outer_smac_15_0);
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170+
if (hash == NETDEV_LAG_HASH_VLAN_SRCMAC) {
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MLX5_SET_TO_ONES(match_definer_format_0,
172+
match_definer_mask,
173+
outer_first_vlan_vid);
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break;
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}
176+
177+
MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
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outer_ethertype);
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MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
180+
outer_dmac_47_16);
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MLX5_SET_TO_ONES(match_definer_format_0, match_definer_mask,
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outer_dmac_15_0);
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break;
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}
185+
186+
return format_id;
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}
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7189
static void set_tt_map(struct mlx5_lag_port_sel *port_sel,
8190
enum netdev_lag_hash hash)
9191
{

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